The Experts below are selected from a list of 56532 Experts worldwide ranked by ideXlab platform
Maher A. Sid-ahmed - One of the best experts on this subject based on the ideXlab platform.
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A Hardware Structure for the automatic selection of multi-level thresholds in digital images
Pattern Recognition, 1992Co-Authors: Maher A. Sid-ahmedAbstract:Abstract Architectures for the selection of levels for thresholding digital images are presented. The architectures are based on an iterative scheme derived by maximizing the variance between regions in the digital image. A new derivation of the iterative scheme is also presented along with a number of examples of image thresholding.
R. Roberts - One of the best experts on this subject based on the ideXlab platform.
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ICASSP - A modular Hardware Structure for digital filtering
ICASSP '80. IEEE International Conference on Acoustics Speech and Signal Processing, 1Co-Authors: M. Arjmand, C. Mullis, R. RobertsAbstract:Good digital filter realizations for Hardware implementation in narrowband filtering applications should have low roundoff noise, low coefficient sensitivity, and freedom from overflow oscillations. The Hardware implementations presented here incorporate the above properties into a highly modular Structure which can perform computations in pipeline fashion. That is, after an initial delay an output sample is obtained for each input sample. The realization and implementations discussed here contain more multipliers than direct form realizations. However, by using shorter word lengths because of their increased performance and distributed arithmetic implementations (instead of multiplier Structures) these implementations can have less total Hardware complexity.
M. Arjmand - One of the best experts on this subject based on the ideXlab platform.
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ICASSP - A modular Hardware Structure for digital filtering
ICASSP '80. IEEE International Conference on Acoustics Speech and Signal Processing, 1Co-Authors: M. Arjmand, C. Mullis, R. RobertsAbstract:Good digital filter realizations for Hardware implementation in narrowband filtering applications should have low roundoff noise, low coefficient sensitivity, and freedom from overflow oscillations. The Hardware implementations presented here incorporate the above properties into a highly modular Structure which can perform computations in pipeline fashion. That is, after an initial delay an output sample is obtained for each input sample. The realization and implementations discussed here contain more multipliers than direct form realizations. However, by using shorter word lengths because of their increased performance and distributed arithmetic implementations (instead of multiplier Structures) these implementations can have less total Hardware complexity.
Zhang Zhi-hui - One of the best experts on this subject based on the ideXlab platform.
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Hardware Structure Analysis of Fuzzy CMAC and Its FPGA Implementation
Computer Engineering, 2007Co-Authors: Zhang Zhi-huiAbstract:This paper proposes a FPGA implementation Structure of a fuzzy CMAC.Compared with other neural networks implemented by FPGA,it contains the learning algorithm which can be employed to realize the on-line learning.The model and the relevant Hardware modules of fuzzy CMAC are analyzed.It implements the fuzzy CMAC based on the above Hardware modules with VHDL.The design is synthesized and tested.The test result shows that the method of the Hardware implementation of the fuzzy CMAC is feasible.The implemented network comprises the characteristics of high speed,good precision and little chip resource.It is an effective method in implementing the module of fuzzy CMAC in SOPC.
Ioannis Andreadis - One of the best experts on this subject based on the ideXlab platform.
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A real-time fuzzy Hardware Structure for disparity map computation
Journal of Real-Time Image Processing, 2010Co-Authors: Christos Georgoulas, Ioannis AndreadisAbstract:Stereo images acquired by a stereo camera setup provide depth estimation of a scene. Numerous machine vision applications deal with retrieval of 3D information. Disparity map recovery from a stereo image pair involves computationally complex algorithms. Previous methods of disparity map computation are mainly restricted to software-based techniques on general-purpose architectures, presenting relatively high execution time. In this paper, a new Hardware-implemented real-time disparity map computation module is realized. This enables a Hardware-based fuzzy inference system parallel-pipelined design, for the overall module, implemented on a single FPGA device with a typical operating frequency of 138 MHz. This provides accurate disparity map computation at a rate of nearly 440 frames per second, given a stereo image pair with a disparity range of 80 pixels and 640 × 480 pixels spatial resolution. The proposed method allows a fast disparity map computational module to be built, enabling a suitable module for real-time stereo vision applications.
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a real time occlusion aware Hardware Structure for disparity map computation
International Conference on Image Analysis and Processing, 2009Co-Authors: Christos Georgoulas, Ioannis AndreadisAbstract:Many machine vision applications deal with depth estimation in a scene. Disparity map recovery from a stereo image pair has been extensively studied by the computer vision community. Previous methods are mainly restricted to software based techniques on general-purpose architectures, presenting relatively high execution time due to the computationally complex algorithms involved. In this paper a new Hardware module suitable for real-time disparity map computation module is realized. This enables a Hardware based occlusion-aware parallel-pipelined design, implemented on a single FPGA device with a typical operating frequency of 511 MHz. It provides accurate disparity map computation at a rate of 768 frames per second, given a stereo image pair with a disparity range of 80 pixels and 640x480 pixel spatial resolution. The proposed method allows a fast disparity map computational module to be built, enabling a suitable module for real-time stereo vision applications.
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Design and Implementation of a Fuzzy-Modified Ant Colony Hardware Structure for Image Retrieval
IEEE Transactions on Systems Man and Cybernetics Part C (Applications and Reviews), 2009Co-Authors: Konstantinos Konstantinidis, Georgios Ch. Sirakoulis, Ioannis AndreadisAbstract:In this paper, a Hardware implementation of a fuzzy modified ant colony processor that is suitable for image retrieval is presented for the first time. The proposed method utilizes three different descriptors in a two stage fuzzy ant algorithm where the query image represents the nest and the database images represent the food. From the Hardware point of view, only a small number of algorithms for Hardware implementation have been reported in the image retrieval literature, since research focuses mainly on possible software solutions and the acceleration of existing algorithms. The proposed digital Hardware Structure is based on a sequence of pipeline stages, while parallel processing is also used in order to minimize computational times. It is capable of performing the extraction and comparison of features from (64times64)-pixel-size color images, although through a simple transformation it can be easily expanded to accommodate images of larger sizes. The architecture of the processor is generic; the units that perform the fuzzy inference can be used with different descriptors than the ones proposed here and can be utilized for other fuzzy applications. It was designed, compiled, and simulated using the Quartus Programmable Logic Development System by the Altera Corporation. The fuzzy processor exhibits a level of inference performance of 800 K fuzzy logic inferences per second with 24 rules, and can be used for real-time applications where the need for short processing times is of the utmost importance.
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CAIP - A New Hardware Structure for Implementation of Soft Morphological Filters
Computer Analysis of Images and Patterns, 1997Co-Authors: Antonios Gasteratos, Ioannis Andreadis, Ph. TsalidesAbstract:A new Hardware Structure for implementation of soft morphological filters is presented in this paper. This is based on the modification of the majority gate technique. A pipelined systolic array architecture suitable to perform real-time soft morphological filtering is presented as an illustrative example. The processing times of the proposed Hardware Structure do not depend on the data window size and its Hardware complexity grows linearly with the number of its inputs.
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An intelligent Hardware Structure for impulse noise suppression
3rd International Symposium on Image and Signal Processing and Analysis 2003. ISPA 2003. Proceedings of the, 1Co-Authors: Gerasimos Louverdis, Ioannis Andreadis, Nikolaos PapamarkosAbstract:In this paper an intelligent Hardware module suitable for the computation of an adaptive median filter (AMF) is presented. The proposed digital Hardware Structure is pipelined and parallel processing is used to minimize computational time. It is capable of processing gray-scale images of 8-bit resolution with 3/spl times/3 or 5/spl times/5-pixel image neighborhoods as options for the computation of the filter output. However, the system can be easily expanded to accommodate windows of larger sizes. The function of the proposed circuitry is to detect the existence of impulse noise in an image neighborhood and apply the median filter operator only when necessary. Moreover, the noise detection procedure can be customized so that a range of pixel values is considered as impulse noise. In this way, the integrity of edge and detail information of the image under process is preserved and blurring is avoided. The proposed digital Structure was implemented in FPGA and it can be used in industrial imaging applications, where fast processing is of the utmost importance. As an example, the time required to perform filtering of a grayscale image of 260/spl times/244 pixels is approximately 7.6 msec. The typical system clock frequency is 65 MHz.
