The Experts below are selected from a list of 228 Experts worldwide ranked by ideXlab platform
Michael Manzke - One of the best experts on this subject based on the ideXlab platform.
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a Hardware Unit for fast sah optimised bvh construction
International Conference on Computer Graphics and Interactive Techniques, 2013Co-Authors: Michael J Doyle, Colin Fowler, Michael ManzkeAbstract:Ray-tracing algorithms are known for producing highly realistic images, but at a significant computational cost. For this reason, a large body of research exists on various techniques for accelerating these costly algorithms. One approach to achieving superior performance which has received comparatively little attention is the design of specialised ray-tracing Hardware. The research that does exist on this topic has consistently demonstrated that significant performance and efficiency gains can be achieved with dedicated microarchitectures. However, previous work on Hardware ray-tracing has focused almost entirely on the traversal and intersection aspects of the pipeline. As a result, the critical aspect of the management and construction of acceleration data-structures remains largely absent from the Hardware literature. We propose that a specialised microarchitecture for this purpose could achieve considerable performance and efficiency improvements over programmable platforms. To this end, we have developed the first dedicated microarchitecture for the construction of binned SAH BVHs. Cycle-accurate simulations show that our design achieves significant improvements in raw performance and in the bandwidth required for construction, as well as large efficiency gains in terms of performance per clock and die area compared to manycore implementations. We conclude that such a design would be useful in the context of a heterogeneous graphics processor, and may help future graphics processor designs to reduce predicted technology-imposed utilisation limits.
Michael J Doyle - One of the best experts on this subject based on the ideXlab platform.
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a Hardware Unit for fast sah optimised bvh construction
International Conference on Computer Graphics and Interactive Techniques, 2013Co-Authors: Michael J Doyle, Colin Fowler, Michael ManzkeAbstract:Ray-tracing algorithms are known for producing highly realistic images, but at a significant computational cost. For this reason, a large body of research exists on various techniques for accelerating these costly algorithms. One approach to achieving superior performance which has received comparatively little attention is the design of specialised ray-tracing Hardware. The research that does exist on this topic has consistently demonstrated that significant performance and efficiency gains can be achieved with dedicated microarchitectures. However, previous work on Hardware ray-tracing has focused almost entirely on the traversal and intersection aspects of the pipeline. As a result, the critical aspect of the management and construction of acceleration data-structures remains largely absent from the Hardware literature. We propose that a specialised microarchitecture for this purpose could achieve considerable performance and efficiency improvements over programmable platforms. To this end, we have developed the first dedicated microarchitecture for the construction of binned SAH BVHs. Cycle-accurate simulations show that our design achieves significant improvements in raw performance and in the bandwidth required for construction, as well as large efficiency gains in terms of performance per clock and die area compared to manycore implementations. We conclude that such a design would be useful in the context of a heterogeneous graphics processor, and may help future graphics processor designs to reduce predicted technology-imposed utilisation limits.
Colin Fowler - One of the best experts on this subject based on the ideXlab platform.
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a Hardware Unit for fast sah optimised bvh construction
International Conference on Computer Graphics and Interactive Techniques, 2013Co-Authors: Michael J Doyle, Colin Fowler, Michael ManzkeAbstract:Ray-tracing algorithms are known for producing highly realistic images, but at a significant computational cost. For this reason, a large body of research exists on various techniques for accelerating these costly algorithms. One approach to achieving superior performance which has received comparatively little attention is the design of specialised ray-tracing Hardware. The research that does exist on this topic has consistently demonstrated that significant performance and efficiency gains can be achieved with dedicated microarchitectures. However, previous work on Hardware ray-tracing has focused almost entirely on the traversal and intersection aspects of the pipeline. As a result, the critical aspect of the management and construction of acceleration data-structures remains largely absent from the Hardware literature. We propose that a specialised microarchitecture for this purpose could achieve considerable performance and efficiency improvements over programmable platforms. To this end, we have developed the first dedicated microarchitecture for the construction of binned SAH BVHs. Cycle-accurate simulations show that our design achieves significant improvements in raw performance and in the bandwidth required for construction, as well as large efficiency gains in terms of performance per clock and die area compared to manycore implementations. We conclude that such a design would be useful in the context of a heterogeneous graphics processor, and may help future graphics processor designs to reduce predicted technology-imposed utilisation limits.
Hemangee K. Kapoor - One of the best experts on this subject based on the ideXlab platform.
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DAC - Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs
Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19, 2019Co-Authors: Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. KapoorAbstract:Network Demultiplexer (Net-Demux) is an essential Hardware Unit in multiple NoCs for traffic distribution between the NoC networks. This paper proposes a novel idea of the placement of Net-Demux at the control plane of switch allocator of the router to improve static power and energy efficiency as compared to conventional data plane placement at the Network Interface (NI).
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Late Breaking Results: Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs
2019Co-Authors: Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. KapoorAbstract:Network Demultiplexer (Net-Demux) is an essential Hardware Unit in multiple NoCs for traffic distribution between the NoC networks. This paper proposes a novel idea of the placement of Net-Demux at the control plane of switch allocator of the router to improve static power and energy efficiency as compared to conventional data plane placement at the Network Interface (NI).
Sonal Yadav - One of the best experts on this subject based on the ideXlab platform.
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DAC - Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs
Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19, 2019Co-Authors: Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. KapoorAbstract:Network Demultiplexer (Net-Demux) is an essential Hardware Unit in multiple NoCs for traffic distribution between the NoC networks. This paper proposes a novel idea of the placement of Net-Demux at the control plane of switch allocator of the router to improve static power and energy efficiency as compared to conventional data plane placement at the Network Interface (NI).
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Late Breaking Results: Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs
2019Co-Authors: Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. KapoorAbstract:Network Demultiplexer (Net-Demux) is an essential Hardware Unit in multiple NoCs for traffic distribution between the NoC networks. This paper proposes a novel idea of the placement of Net-Demux at the control plane of switch allocator of the router to improve static power and energy efficiency as compared to conventional data plane placement at the Network Interface (NI).
