The Experts below are selected from a list of 129 Experts worldwide ranked by ideXlab platform
Xiangke Liao - One of the best experts on this subject based on the ideXlab platform.
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RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router
IEEE Transactions on Parallel and Distributed Systems, 2018Co-Authors: Dezun Dong, Xiangke LiaoAbstract:Traditional input-queued routers in network-on-chips (NoCs) only have a small number of virtual channels (VCs) and packets in a VC are organized in a fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. Since Switch allocation is the critical pipeline stage in on-chip routers, HoL blocking significantly degrades the performance of NoCs. In this paper, we propose to schedule packets in input buffers utilizing reorder buffer (RoB) techniques. We design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packets. RoBs reduce the conflicts in Switch allocation and mitigate the HoL blocking and thus improve the NoC performance. However, it is hard to reorder all the units in a VC due to circuit complexity and power overhead. We propose RoB-Router, which leverages elastic RoBs in VCs to only allow a part of a VC to act as RoB. RoB-Router automatically determines the length of RoB in a VC based on the number of buffered flits. This design minimizes the resource while achieving excellent efficiency. Furthermore, we propose two independent methods to improve the performance of RoB-Router. One is to optimize the packet order in input buffers by redesigning VC allocation strategy. The other combines RoB-Router with current most efficient Switch Allocator TS-Router. We perform evaluations and the results show that our design can achieve 46 and 15.7 percent performance improvement in packet latency under synthetic traffic and traces from PARSEC than TS-Router, and the cost of energy and area is moderate. Additionally, average packet latency reduction by our two improving methods under uniform traffic is 13 and 17 percent respectively.
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ACM TUR-C - Exploiting contention and congestion aware Switch allocation in network-on-chips
Proceedings of the ACM Turing 50th Celebration Conference - China on - ACM TUR-C '17, 2017Co-Authors: Dezun Dong, Xiangke LiaoAbstract:Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting congestion and contention information to load balance the traffic. However, most prior works do not consider balancing the traffic load during Switch allocation. Due to the lack of congestion information in Switch allocation stage, Switch Allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of Switch. In this paper, we propose to add the congestion and contention information into the Switch allocation process and design an efficient on-chip Switching strategy which utilizes the contention and congestion information to load balance the traffic and achieve efficient Switch allocation. To further enhance the performance of our design, we carefully design our Switch allocation strategy to balance the trade-off between traffic load balance and the matching efficiency in Switch allocation. We evaluate our design under synthetic traffic and trace of parsec benchmarks. Our evaluations show this mechanism achieves optimal latency compared to best previous Switch allocation strategies.
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rob router low latency network on chip router microarchitecture using reorder buffer
High Performance Interconnects, 2016Co-Authors: Cunlu Li, Dezun Dong, Xiangke Liao, Ji Wu, Fei LeiAbstract:Switch allocation is the critical pipeline stage for network-on-chips (NoCs) and it is influenced by the order of packets in input buffers. Traditional input-queued routers in NoCs only have a small number of virtual channels (VCs) and the packets in a VC are organized in fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. HoL blocking significantly degrades the efficiency of Switch allocation as well as the performance of NoCs. In this paper, we propose to utilize reorder buffer (RoB) techniques to mitigate HoL blocking and accelerate Switch allocation and thus reduce the latency of NoCs. We propose to design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packet. RoBs reduce the conflicts in Switch allocation and can efficiently increase matching number in Switch allocation. We design RoB-Router based on traditional input-queued routers in a lightweight fashion considering the trade-off between performance and cost. Our design can be extended to most state-of-the-art input-queued routers. Evaluation results show that RoB-Router can achieve 46% and 15.7% performance improvement in packet latency under synthetic traffic and traces from PARSEC than current most efficient Switch Allocator TS-Router, and the cost of energy and area is moderate.
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Hot Interconnects - RoB-Router: Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer
2016 IEEE 24th Annual Symposium on High-Performance Interconnects (HOTI), 2016Co-Authors: Dezun Dong, Xiangke Liao, Fei LeiAbstract:Switch allocation is the critical pipeline stage for network-on-chips (NoCs) and it is influenced by the order of packets in input buffers. Traditional input-queued routers in NoCs only have a small number of virtual channels (VCs) and the packets in a VC are organized in fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. HoL blocking significantly degrades the efficiency of Switch allocation as well as the performance of NoCs. In this paper, we propose to utilize reorder buffer (RoB) techniques to mitigate HoL blocking and accelerate Switch allocation and thus reduce the latency of NoCs. We propose to design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packet. RoBs reduce the conflicts in Switch allocation and can efficiently increase matching number in Switch allocation. We design RoB-Router based on traditional input-queued routers in a lightweight fashion considering the trade-off between performance and cost. Our design can be extended to most state-of-the-art input-queued routers. Evaluation results show that RoB-Router can achieve 46% and 15.7% performance improvement in packet latency under synthetic traffic and traces from PARSEC than current most efficient Switch Allocator TS-Router, and the cost of energy and area is moderate.
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ICCD - CCAS: Contention and congestion aware Switch allocation for network-on-chips
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Co-Authors: Dezun Dong, Xiangke Liao, Fei LeiAbstract:Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting contention and congestion information to load balance the traffic. However, most prior works do not consider balancing the traffic load during Switch allocation. Due to the lack of congestion information in Switch allocation stage, Switch Allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of Switch. In this paper, we propose CCAS, a new Switch allocation strategy to add the contention and congestion information into the Switching process to load balance the traffic and achieve efficient Switch allocation. We carefully design CCAS to balance the trade-off between traffic load balance and the matching efficiency in Switch allocation. We evaluate our design under synthetic traffic and traces of PARSEC benchmarks. Our evaluations show that CCAS can achieve remarkable latency reduction compared to other Switch allocation strategies.
Dezun Dong - One of the best experts on this subject based on the ideXlab platform.
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RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router
IEEE Transactions on Parallel and Distributed Systems, 2018Co-Authors: Dezun Dong, Xiangke LiaoAbstract:Traditional input-queued routers in network-on-chips (NoCs) only have a small number of virtual channels (VCs) and packets in a VC are organized in a fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. Since Switch allocation is the critical pipeline stage in on-chip routers, HoL blocking significantly degrades the performance of NoCs. In this paper, we propose to schedule packets in input buffers utilizing reorder buffer (RoB) techniques. We design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packets. RoBs reduce the conflicts in Switch allocation and mitigate the HoL blocking and thus improve the NoC performance. However, it is hard to reorder all the units in a VC due to circuit complexity and power overhead. We propose RoB-Router, which leverages elastic RoBs in VCs to only allow a part of a VC to act as RoB. RoB-Router automatically determines the length of RoB in a VC based on the number of buffered flits. This design minimizes the resource while achieving excellent efficiency. Furthermore, we propose two independent methods to improve the performance of RoB-Router. One is to optimize the packet order in input buffers by redesigning VC allocation strategy. The other combines RoB-Router with current most efficient Switch Allocator TS-Router. We perform evaluations and the results show that our design can achieve 46 and 15.7 percent performance improvement in packet latency under synthetic traffic and traces from PARSEC than TS-Router, and the cost of energy and area is moderate. Additionally, average packet latency reduction by our two improving methods under uniform traffic is 13 and 17 percent respectively.
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ACM TUR-C - Exploiting contention and congestion aware Switch allocation in network-on-chips
Proceedings of the ACM Turing 50th Celebration Conference - China on - ACM TUR-C '17, 2017Co-Authors: Dezun Dong, Xiangke LiaoAbstract:Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting congestion and contention information to load balance the traffic. However, most prior works do not consider balancing the traffic load during Switch allocation. Due to the lack of congestion information in Switch allocation stage, Switch Allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of Switch. In this paper, we propose to add the congestion and contention information into the Switch allocation process and design an efficient on-chip Switching strategy which utilizes the contention and congestion information to load balance the traffic and achieve efficient Switch allocation. To further enhance the performance of our design, we carefully design our Switch allocation strategy to balance the trade-off between traffic load balance and the matching efficiency in Switch allocation. We evaluate our design under synthetic traffic and trace of parsec benchmarks. Our evaluations show this mechanism achieves optimal latency compared to best previous Switch allocation strategies.
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rob router low latency network on chip router microarchitecture using reorder buffer
High Performance Interconnects, 2016Co-Authors: Cunlu Li, Dezun Dong, Xiangke Liao, Ji Wu, Fei LeiAbstract:Switch allocation is the critical pipeline stage for network-on-chips (NoCs) and it is influenced by the order of packets in input buffers. Traditional input-queued routers in NoCs only have a small number of virtual channels (VCs) and the packets in a VC are organized in fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. HoL blocking significantly degrades the efficiency of Switch allocation as well as the performance of NoCs. In this paper, we propose to utilize reorder buffer (RoB) techniques to mitigate HoL blocking and accelerate Switch allocation and thus reduce the latency of NoCs. We propose to design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packet. RoBs reduce the conflicts in Switch allocation and can efficiently increase matching number in Switch allocation. We design RoB-Router based on traditional input-queued routers in a lightweight fashion considering the trade-off between performance and cost. Our design can be extended to most state-of-the-art input-queued routers. Evaluation results show that RoB-Router can achieve 46% and 15.7% performance improvement in packet latency under synthetic traffic and traces from PARSEC than current most efficient Switch Allocator TS-Router, and the cost of energy and area is moderate.
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Hot Interconnects - RoB-Router: Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer
2016 IEEE 24th Annual Symposium on High-Performance Interconnects (HOTI), 2016Co-Authors: Dezun Dong, Xiangke Liao, Fei LeiAbstract:Switch allocation is the critical pipeline stage for network-on-chips (NoCs) and it is influenced by the order of packets in input buffers. Traditional input-queued routers in NoCs only have a small number of virtual channels (VCs) and the packets in a VC are organized in fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. HoL blocking significantly degrades the efficiency of Switch allocation as well as the performance of NoCs. In this paper, we propose to utilize reorder buffer (RoB) techniques to mitigate HoL blocking and accelerate Switch allocation and thus reduce the latency of NoCs. We propose to design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packet. RoBs reduce the conflicts in Switch allocation and can efficiently increase matching number in Switch allocation. We design RoB-Router based on traditional input-queued routers in a lightweight fashion considering the trade-off between performance and cost. Our design can be extended to most state-of-the-art input-queued routers. Evaluation results show that RoB-Router can achieve 46% and 15.7% performance improvement in packet latency under synthetic traffic and traces from PARSEC than current most efficient Switch Allocator TS-Router, and the cost of energy and area is moderate.
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ICCD - CCAS: Contention and congestion aware Switch allocation for network-on-chips
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Co-Authors: Dezun Dong, Xiangke Liao, Fei LeiAbstract:Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting contention and congestion information to load balance the traffic. However, most prior works do not consider balancing the traffic load during Switch allocation. Due to the lack of congestion information in Switch allocation stage, Switch Allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of Switch. In this paper, we propose CCAS, a new Switch allocation strategy to add the contention and congestion information into the Switching process to load balance the traffic and achieve efficient Switch allocation. We carefully design CCAS to balance the trade-off between traffic load balance and the matching efficiency in Switch allocation. We evaluate our design under synthetic traffic and traces of PARSEC benchmarks. Our evaluations show that CCAS can achieve remarkable latency reduction compared to other Switch allocation strategies.
Fei Lei - One of the best experts on this subject based on the ideXlab platform.
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rob router low latency network on chip router microarchitecture using reorder buffer
High Performance Interconnects, 2016Co-Authors: Cunlu Li, Dezun Dong, Xiangke Liao, Ji Wu, Fei LeiAbstract:Switch allocation is the critical pipeline stage for network-on-chips (NoCs) and it is influenced by the order of packets in input buffers. Traditional input-queued routers in NoCs only have a small number of virtual channels (VCs) and the packets in a VC are organized in fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. HoL blocking significantly degrades the efficiency of Switch allocation as well as the performance of NoCs. In this paper, we propose to utilize reorder buffer (RoB) techniques to mitigate HoL blocking and accelerate Switch allocation and thus reduce the latency of NoCs. We propose to design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packet. RoBs reduce the conflicts in Switch allocation and can efficiently increase matching number in Switch allocation. We design RoB-Router based on traditional input-queued routers in a lightweight fashion considering the trade-off between performance and cost. Our design can be extended to most state-of-the-art input-queued routers. Evaluation results show that RoB-Router can achieve 46% and 15.7% performance improvement in packet latency under synthetic traffic and traces from PARSEC than current most efficient Switch Allocator TS-Router, and the cost of energy and area is moderate.
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Hot Interconnects - RoB-Router: Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer
2016 IEEE 24th Annual Symposium on High-Performance Interconnects (HOTI), 2016Co-Authors: Dezun Dong, Xiangke Liao, Fei LeiAbstract:Switch allocation is the critical pipeline stage for network-on-chips (NoCs) and it is influenced by the order of packets in input buffers. Traditional input-queued routers in NoCs only have a small number of virtual channels (VCs) and the packets in a VC are organized in fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the Switch Allocator. HoL blocking significantly degrades the efficiency of Switch allocation as well as the performance of NoCs. In this paper, we propose to utilize reorder buffer (RoB) techniques to mitigate HoL blocking and accelerate Switch allocation and thus reduce the latency of NoCs. We propose to design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packet. RoBs reduce the conflicts in Switch allocation and can efficiently increase matching number in Switch allocation. We design RoB-Router based on traditional input-queued routers in a lightweight fashion considering the trade-off between performance and cost. Our design can be extended to most state-of-the-art input-queued routers. Evaluation results show that RoB-Router can achieve 46% and 15.7% performance improvement in packet latency under synthetic traffic and traces from PARSEC than current most efficient Switch Allocator TS-Router, and the cost of energy and area is moderate.
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ICCD - CCAS: Contention and congestion aware Switch allocation for network-on-chips
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Co-Authors: Dezun Dong, Xiangke Liao, Fei LeiAbstract:Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting contention and congestion information to load balance the traffic. However, most prior works do not consider balancing the traffic load during Switch allocation. Due to the lack of congestion information in Switch allocation stage, Switch Allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of Switch. In this paper, we propose CCAS, a new Switch allocation strategy to add the contention and congestion information into the Switching process to load balance the traffic and achieve efficient Switch allocation. We carefully design CCAS to balance the trade-off between traffic load balance and the matching efficiency in Switch allocation. We evaluate our design under synthetic traffic and traces of PARSEC benchmarks. Our evaluations show that CCAS can achieve remarkable latency reduction compared to other Switch allocation strategies.
Hemangee K. Kapoor - One of the best experts on this subject based on the ideXlab platform.
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DAC - Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs
Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19, 2019Co-Authors: Sonal Yadav, Manoj Singh Gaur, Vijay Laxmi, Hemangee K. KapoorAbstract:Network Demultiplexer (Net-Demux) is an essential hardware unit in multiple NoCs for traffic distribution between the NoC networks. This paper proposes a novel idea of the placement of Net-Demux at the control plane of Switch Allocator of the router to improve static power and energy efficiency as compared to conventional data plane placement at the Network Interface (NI).
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Late Breaking Results: Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs
2019Co-Authors: Sonal Yadav, Manoj Singh Gaur, Vijay Laxmi, Hemangee K. KapoorAbstract:Network Demultiplexer (Net-Demux) is an essential hardware unit in multiple NoCs for traffic distribution between the NoC networks. This paper proposes a novel idea of the placement of Net-Demux at the control plane of Switch Allocator of the router to improve static power and energy efficiency as compared to conventional data plane placement at the Network Interface (NI).
Jose A. Antonino-daviu - One of the best experts on this subject based on the ideXlab platform.
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Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip
Electronics, 2020Co-Authors: Ayaz Hussain, Muhammad Irfan, Naveed Khan Baloch, Umar Draz, Tariq Ali, Adam Glowacz, Larisa Dunai, Jose A. Antonino-daviuAbstract:The router plays an important role in communication among different processing cores in on-chip networks. Technology scaling on one hand has enabled the designers to integrate multiple processing components on a single chip; on the other hand, it becomes the reason for faults. A generic router consists of the buffers and pipeline stages. A single fault may result in an undesirable situation of degraded performance or a whole chip may stop working. Therefore, it is necessary to provide permanent fault tolerance to all the components of the router. In this paper, we propose a mechanism that can tolerate permanent faults that occur in the router. We exploit the fault-tolerant techniques of resource sharing and paring between components for the input port unit and routing computation (RC) unit, the resource borrowing for virtual channel Allocator (VA) and multiple paths for Switch Allocator (SA) and crossbar (XB). The experimental results and analysis show that the proposed mechanism enhances the reliability of the router architecture towards permanent faults at the cost of 29% area overhead. The proposed router architecture achieves the highest Silicon Protection Factor (SPF) metric, which is 24.8 as compared to the state-of-the-art fault-tolerant architectures. It incurs an increase in latency for SPLASH2 and PARSEC benchmark traffics, which is minimal as compared to the baseline router.
