The Experts below are selected from a list of 160818 Experts worldwide ranked by ideXlab platform
Byoung Hun Lee - One of the best experts on this subject based on the ideXlab platform.
-
Improvement of metal gate/High-K Dielectric CMOSFETs characteristics by neutral beam etching of metal gate
Solid-State Electronics, 2013Co-Authors: K.s. Min, Chanro Park, C. Y. Kang, C.s. Park, B.j. Park, Yong-seok Kim, Byoung Hun Lee, Jack C. Lee, Gennadi Bersuker, Paul KirschAbstract:Abstract For the metal gate patterning of metal gate/High-K Dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate Dielectric of CMOSFEETs.
-
Stress field analysis to understand the breakdown characteristics of stacked High-K Dielectrics
Applied Physics Letters, 2009Co-Authors: Byoung Hun Lee, C. Y. Kang, Rino Choi, Hi Deok Lee, Gennadi BersukerAbstract:The validity of the stress biases used in reliability studies of High-K Dielectric is discussed by analyzing the stress biases used in previous works. For single layer Dielectrics, stress biases near the time zero Dielectric breakdown point have been used to reduce the test time. However, stacked Dielectrics need a more careful approach to avoid overstress. We show that the majority of earlier work on the reliability of High-K Dielectric used high electric field and those results may not be optimal for predicting intrinsic reliability characteristics. A simple guideline to avoid overstress is provided.
-
Metal Electrode/High- $k$ Dielectric Gate-Stack Technology for Power Management
IEEE Transactions on Electron Devices, 2008Co-Authors: Byoung Hun Lee, Seung Chul Song, Rino Choi, Paul KirschAbstract:High-K Dielectrics have been intensively investigated during the last decade, and their performance as a gate Dielectric has been improved to the level of conventional SiO2-based gate Dielectric at an equivalent oxide thickness (EOT) ~1 nm. The understanding on metal electrodes and their interaction with the underlying High-K Dielectric has been expanded, and various CMOS device results with metal electrode/High-K gate Dielectric stacks have been reported, indicating the maturity of this technology. The next challenges lie in scaling the gate stack to 0.5-nm EOT to extend the usage of the metal electrode/High-K gate Dielectric stacks to future technology generations. A new class of High-K Dielectric that has a Dielectric constant higher than 26 and a barrier height of ~5.0 eV and above will be needed to achieve this target. Recent progress in this so-called higher k Dielectric research is summarized, and its benefit to the gate leakage current is discussed. This paper also reviews various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.
-
spectroscopic ellipsometry characterization of high k Dielectric hfo2 thin films and the high temperature annealing effects on their optical properties
Applied Physics Letters, 2002Co-Authors: Yong J Cho, Byoung Hun Lee, Nhan V Nguyen, Curt A Richter, James R Ehrstein, Jack C. LeeAbstract:The optical properties of a set of High-K Dielectric HfO2 films annealed at various high temperatures were determined by spectroscopic ellipsometry. The results show that the characteristics of the Dielectric functions of these films are strongly affected by high temperature annealing. For a sample annealed at 600 °C, the film becomes polycrystalline, and its Dielectric function displays a distinctive peak at 5.9 eV. On the other hand, the film remains amorphous without the 5.9 eV feature after 500 °C annealing. To model the Dielectric functions, the Tauc–Lorentz dispersion was successfully adopted for these amorphous and polycrystalline films. The absorption edge was observed to shift to a higher energy at a high temperature annealing. Defects in the films were shown to relate to the appearance of a band tail above the absorption edge, and they appear to diminish with high temperature annealing.
Jack C. Lee - One of the best experts on this subject based on the ideXlab platform.
-
Improvement of metal gate/High-K Dielectric CMOSFETs characteristics by neutral beam etching of metal gate
Solid-State Electronics, 2013Co-Authors: K.s. Min, Chanro Park, C. Y. Kang, C.s. Park, B.j. Park, Yong-seok Kim, Byoung Hun Lee, Jack C. Lee, Gennadi Bersuker, Paul KirschAbstract:Abstract For the metal gate patterning of metal gate/High-K Dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate Dielectric of CMOSFEETs.
-
spectroscopic ellipsometry characterization of high k Dielectric hfo2 thin films and the high temperature annealing effects on their optical properties
Applied Physics Letters, 2002Co-Authors: Yong J Cho, Byoung Hun Lee, Nhan V Nguyen, Curt A Richter, James R Ehrstein, Jack C. LeeAbstract:The optical properties of a set of High-K Dielectric HfO2 films annealed at various high temperatures were determined by spectroscopic ellipsometry. The results show that the characteristics of the Dielectric functions of these films are strongly affected by high temperature annealing. For a sample annealed at 600 °C, the film becomes polycrystalline, and its Dielectric function displays a distinctive peak at 5.9 eV. On the other hand, the film remains amorphous without the 5.9 eV feature after 500 °C annealing. To model the Dielectric functions, the Tauc–Lorentz dispersion was successfully adopted for these amorphous and polycrystalline films. The absorption edge was observed to shift to a higher energy at a high temperature annealing. Defects in the films were shown to relate to the appearance of a band tail above the absorption edge, and they appear to diminish with high temperature annealing.
Jiafei Yao - One of the best experts on this subject based on the ideXlab platform.
-
The New Structure and Analytical Model of a High-Voltage Interconnection Shielding Structure With High- k Dielectric Pillar
IEEE Transactions on Electron Devices, 2020Co-Authors: Yufeng Guo, Jiafei Yao, Jun Zhang, Kemeng YangAbstract:The high-voltage interconnection (HVI) effect induces electric field crowding near the source region of power lateral double diffused metal oxide semiconductor field effect transistors (LDMOSs) and, therefore, weakens its breakdown voltage (BV) characteristic. To suppress such a detrimental effect, a novel HVI structure with a high- ${k}$ Dielectric pillar beneath the HVI metal line is proposed. An analytical model is proposed to reveal the mechanism of the proposed structure and explain the effects of the parameters of the structure. The analytical model indicates that the high- ${k}$ Dielectric pillar eliminates the electric field crowding near the source, promotes the depletion of the drift region, and avoids the premature breakdown. Meanwhile, due to the existence of the high- ${k}$ Dielectric pillar, the surface electric field profile in the drift region can be modulated, and the influence of HVI can be effectively suppressed. Thus, a higher BV is obtained. The simulation results indicate that the proposed structure presents better BV, which is the same as that of the reduced surface field (RESURF) structure without HVI.
-
Equivalent model and limit for the SOI lateral power device using High-K Dielectric
Results in Physics, 2019Co-Authors: Jiafei Yao, Yufeng Guo, Yu Deng, Kemeng Yang, Tian XiaAbstract:Abstract This paper presents a simple and clear equivalent model to investigate the SOI lateral power device using High-K Dielectric (HK device). The proposed model can accurately characterize the electric field and facilitate the obtainment of optimal breakdown voltage (BV). The analytical results of the equivalent model are well matched with the simulation results from TCAD simulator, showing the validity of the proposed model. The analytical equations of vertical and lateral breakdown voltages demonstrate the breakdown mechanism of the HK device, and indicate that the BV can be effectively improved using High-K Dielectric. The proposed model also expresses the optimal doping concentration of the drift region for guiding the design of the HK device. Furthermore, a limit is theoretically derived to predict the relationship between the specific on-resistance ( R on , s p ) and BV of the HK device.
-
Analytical Model for the SOI Lateral Power Device With Step Width Technique and High- ${k}$ Dielectric
IEEE Transactions on Electron Devices, 2019Co-Authors: Jiafei Yao, Yufeng Guo, Kemeng Yang, Jun Zhang, Tian XiaAbstract:An analytical model is proposed in this paper for optimizing the breakdown voltage (BV) and drift region doping concentration of a silicon-on-insulator (SOI) lateral power device with step width technique and high- ${k}$ Dielectric (SWHK device). By solving the 3-D Poisson equation, the analytical potential and the electric field distribution are investigated. The optimal width of the silicon region of each zone is calculated to obtain the maximum BV and optimal drift region doping concentration. The analytical results are well matched with the simulation results, confirming the validity of the present model. The proposed analytical model reveals the influence of step number and permittivity of high- ${k}$ Dielectric on the performances of the SWHK device and provides guidance for the optimal design of the SWHK device.
Kemeng Yang - One of the best experts on this subject based on the ideXlab platform.
-
The New Structure and Analytical Model of a High-Voltage Interconnection Shielding Structure With High- k Dielectric Pillar
IEEE Transactions on Electron Devices, 2020Co-Authors: Yufeng Guo, Jiafei Yao, Jun Zhang, Kemeng YangAbstract:The high-voltage interconnection (HVI) effect induces electric field crowding near the source region of power lateral double diffused metal oxide semiconductor field effect transistors (LDMOSs) and, therefore, weakens its breakdown voltage (BV) characteristic. To suppress such a detrimental effect, a novel HVI structure with a high- ${k}$ Dielectric pillar beneath the HVI metal line is proposed. An analytical model is proposed to reveal the mechanism of the proposed structure and explain the effects of the parameters of the structure. The analytical model indicates that the high- ${k}$ Dielectric pillar eliminates the electric field crowding near the source, promotes the depletion of the drift region, and avoids the premature breakdown. Meanwhile, due to the existence of the high- ${k}$ Dielectric pillar, the surface electric field profile in the drift region can be modulated, and the influence of HVI can be effectively suppressed. Thus, a higher BV is obtained. The simulation results indicate that the proposed structure presents better BV, which is the same as that of the reduced surface field (RESURF) structure without HVI.
-
Equivalent model and limit for the SOI lateral power device using High-K Dielectric
Results in Physics, 2019Co-Authors: Jiafei Yao, Yufeng Guo, Yu Deng, Kemeng Yang, Tian XiaAbstract:Abstract This paper presents a simple and clear equivalent model to investigate the SOI lateral power device using High-K Dielectric (HK device). The proposed model can accurately characterize the electric field and facilitate the obtainment of optimal breakdown voltage (BV). The analytical results of the equivalent model are well matched with the simulation results from TCAD simulator, showing the validity of the proposed model. The analytical equations of vertical and lateral breakdown voltages demonstrate the breakdown mechanism of the HK device, and indicate that the BV can be effectively improved using High-K Dielectric. The proposed model also expresses the optimal doping concentration of the drift region for guiding the design of the HK device. Furthermore, a limit is theoretically derived to predict the relationship between the specific on-resistance ( R on , s p ) and BV of the HK device.
-
Analytical Model for the SOI Lateral Power Device With Step Width Technique and High- ${k}$ Dielectric
IEEE Transactions on Electron Devices, 2019Co-Authors: Jiafei Yao, Yufeng Guo, Kemeng Yang, Jun Zhang, Tian XiaAbstract:An analytical model is proposed in this paper for optimizing the breakdown voltage (BV) and drift region doping concentration of a silicon-on-insulator (SOI) lateral power device with step width technique and high- ${k}$ Dielectric (SWHK device). By solving the 3-D Poisson equation, the analytical potential and the electric field distribution are investigated. The optimal width of the silicon region of each zone is calculated to obtain the maximum BV and optimal drift region doping concentration. The analytical results are well matched with the simulation results, confirming the validity of the present model. The proposed analytical model reveals the influence of step number and permittivity of high- ${k}$ Dielectric on the performances of the SWHK device and provides guidance for the optimal design of the SWHK device.
Tian Xia - One of the best experts on this subject based on the ideXlab platform.
-
Equivalent model and limit for the SOI lateral power device using High-K Dielectric
Results in Physics, 2019Co-Authors: Jiafei Yao, Yufeng Guo, Yu Deng, Kemeng Yang, Tian XiaAbstract:Abstract This paper presents a simple and clear equivalent model to investigate the SOI lateral power device using High-K Dielectric (HK device). The proposed model can accurately characterize the electric field and facilitate the obtainment of optimal breakdown voltage (BV). The analytical results of the equivalent model are well matched with the simulation results from TCAD simulator, showing the validity of the proposed model. The analytical equations of vertical and lateral breakdown voltages demonstrate the breakdown mechanism of the HK device, and indicate that the BV can be effectively improved using High-K Dielectric. The proposed model also expresses the optimal doping concentration of the drift region for guiding the design of the HK device. Furthermore, a limit is theoretically derived to predict the relationship between the specific on-resistance ( R on , s p ) and BV of the HK device.
-
Analytical Model for the SOI Lateral Power Device With Step Width Technique and High- ${k}$ Dielectric
IEEE Transactions on Electron Devices, 2019Co-Authors: Jiafei Yao, Yufeng Guo, Kemeng Yang, Jun Zhang, Tian XiaAbstract:An analytical model is proposed in this paper for optimizing the breakdown voltage (BV) and drift region doping concentration of a silicon-on-insulator (SOI) lateral power device with step width technique and high- ${k}$ Dielectric (SWHK device). By solving the 3-D Poisson equation, the analytical potential and the electric field distribution are investigated. The optimal width of the silicon region of each zone is calculated to obtain the maximum BV and optimal drift region doping concentration. The analytical results are well matched with the simulation results, confirming the validity of the present model. The proposed analytical model reveals the influence of step number and permittivity of high- ${k}$ Dielectric on the performances of the SWHK device and provides guidance for the optimal design of the SWHK device.