The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Tomasz Czajkowski - One of the best experts on this subject based on the ideXlab platform.
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High Level Synthesis of software customizable floating point cores
Design Automation and Test in Europe, 2018Co-Authors: Samridhi Bansal, Tomasz Czajkowski, Hsuan Hsiao, Jason H AndersonAbstract:Parameterized cores with fixed capabilities are typically used for floating-point (FP) operations on FPGAs. However, such standard cores can be over provisioned or lack specific specializations as required by applications. We consider FP cores described in the C language, synthesized to hardware using the LegUp High-Level Synthesis (HLS) tool [1]. Their software specification permits straightforward customization to non-compliant variants having superior area and performance characteristics, such as reduced-precision floating point, or cores without full IEEE 754 exceptions support. We create and evaluate the IEEE 754 FP standard cores for the key operations of addition, subtraction, division and multiplication, targeted to an FPGA and compare with widely used optimized RTL FP cores from Altera [7] and FloPoCo [3]. The software-specified HLS-generated cores are surprisingly close to the optimized RTL cores in terms of area/performance, and superior in certain cases, such as FP division.
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legup an open source High Level Synthesis tool for fpga based processor accelerator systems
ACM Transactions in Embedded Computing Systems, 2013Co-Authors: Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Stephen D Brown, Tomasz Czajkowski, Jason H AndersonAbstract:It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this article, we introduce a new High-Level Synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixed-sized multidimensional arrays, structs, global variables, and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial High-Level Synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software codesign space by varying the amount of a program that runs in software versus hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of High-Level Synthesis topics.
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From software to accelerators with LegUp High-Level Synthesis
2013 International Conference on Compilers Architecture and Synthesis for Embedded Systems CASES 2013, 2013Co-Authors: Andrew Canis, Jia Jun Qin, B Fort, Michael Gort, Ruolong Lian, Nazanin Calagar, Qijing Huang, Jongsok Choi, Mark Aldham, Tomasz CzajkowskiAbstract:Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source High-Level Synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
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impact of fpga architecture on resource sharing in High Level Synthesis
Field Programmable Gate Arrays, 2012Co-Authors: Stefan Hadjis, Andrew Canis, Jongsok Choi, Jason H Anderson, Stephen D Brown, Kevin Nam, Tomasz CzajkowskiAbstract:Resource sharing is a key area-reduction approach in High-Level Synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the High-Level circuit specification. We show that the utility of sharing depends on the underlying FPGA logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial FPGA families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs).
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legup High Level Synthesis for fpga based processor accelerator systems
Field Programmable Gate Arrays, 2011Co-Authors: Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason H Anderson, Stephen D Brown, Tomasz CzajkowskiAbstract:In this paper, we introduce a new open source High-Level Synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. Results show that the tool produces hardware solutions of comparable quality to a commercial High-Level Synthesis tool.
Luca P Carloni - One of the best experts on this subject based on the ideXlab platform.
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High Level Synthesis of accelerators in embedded scalable platforms
Asia and South Pacific Design Automation Conference, 2016Co-Authors: Paolo Mantovani, Giuseppe Di Guglielmo, Luca P CarloniAbstract:Embedded scalable platforms combine a flexible socketed architecture for heterogeneous system-on-chip (SoC) design and a companion system-Level design methodology. The architecture supports the rapid integration of processor cores with many specialized hardware accelerators. The methodology simplifies the design, integration, and programming of the heterogeneous components in the SoC. In particular, it raises the Level of abstraction in the design process and guides designers in the application of High-Level Synthesis (HLS) tools. HLS enables a more efficient design of accelerators with a focus on their algorithmic properties, a broader exploration of their design space, and a more productive reuse across many different SoC projects.
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system Level memory optimization for High Level Synthesis of component based socs
International Conference on Hardware Software Codesign and System Synthesis, 2014Co-Authors: Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P CarloniAbstract:The design of specialized accelerators is essential to the success of many modern Systems-on-Chip. Electronic system-Level design methodologies and High-Level Synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an accelerator. To address these limitations, we present a novel methodology to automatically derive the memory sub-systems of SoC accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the accelerator specifications. We illustrate its effectiveness by presenting experimental results on the design of two accelerators for a High-performance embedded application.
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compositional system Level design exploration with planning of High Level Synthesis
Design Automation and Test in Europe, 2012Co-Authors: Hungyi Liu, Michele Petracca, Luca P CarloniAbstract:The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-Level modeling (TLM), High-Level Synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration we present three main contributions: a concise library format for characterization and reuse of components specified in High-Level languages like SystemC; an algorithm to prune alternative implementations of a component given the context of a specific SoC design; and an algorithm that explores compositionally the design space of the SoC and produces a detailed plan to run High-Level Synthesis on its components for the final implementation. The two algorithms are computationally efficient and enable an effective parallelization of the Synthesis runs. Through a case study, we show how our methodology returns the essential properties of the design space at the system Level by combining the information from the library of components and by identifying automatically those having the most critical impact on the overall design.
Jason Cong - One of the best experts on this subject based on the ideXlab platform.
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rapid cycle accurate simulator for High Level Synthesis
arXiv: Hardware Architecture, 2018Co-Authors: Yuze Chi, Jason Cong, Youngkyu Choi, Jie WangAbstract:A large semantic gap between the High-Level Synthesis (HLS) design and the low-Level (on-board or RTL) simulation environment often creates a barrier for those who are not FPGA experts. Moreover, such low-Level simulation takes a long time to complete. Software-based HLS simulators can help bridge this gap and accelerate the simulation process; however, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve this correctness issue while maintaining the High speed of a software-based simulator, this paper proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract the scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. Experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.
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resource aware throughput optimization for High Level Synthesis
Field Programmable Gate Arrays, 2015Co-Authors: Peng Zhang, Louisnoel Pouchet, Jason CongAbstract:With the emergence of robust High-Level Synthesis tools to automatically transform codes written in High-Level languages into RTL implementations, the programming productivity when Synthesising accelerators improves significantly. However, although the state-of-the-art High-Level Synthesis tools can offer High-quality designs for simple nested loop kernels, there is still a significant performance gap between the synthesized and the optimal design for real world complex applications with multiple loops. In this work we first demonstrate that maximizing the throughput of each individual loop is not always the most efficient approach to achieving the maximum system-Level throughput. More area efficient non-fully pipelined design variants may outperform the fully-pipelined version by enabling larger degrees of parallelism. We develop an algorithm to determine the optimal resource usage and initiation intervals for each loop in the applications to achieve maximum throughput within a given area budget. We report experimental results on eight applications, showing an average of 31% performance speedup over state-of-the-art HLS solutions.
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improving polyhedral code generation for High Level Synthesis
International Conference on Hardware Software Codesign and System Synthesis, 2013Co-Authors: Wei Zuo, Deming Chen, Louisnoel Pouchet, Shunan Zhong, Jason CongAbstract:High-Level Synthesis (HLS) tools are now capable of generating High-quality RTL codes for a number of programs. Nevertheless, for best performance aggressive program transformations are still required to exploit data reuse and enable communication/computation overlap. The polyhedral compilation framework has shown great promise in this area with the development of HLS-specific polyhedral transformation techniques and tools. However, all these techniques rely on polyhedral code generation to translate a schedule for the program's operations into an actual C code that is input to the HLS tool. In this work we study the changes to the state-of-the-art polyhedral code generator CLooG which are required to tailor it for HLS purposes. In particular, we develop various techniques to significantly improve resource utilization on the FPGA. We also develop a complete technique geared towards effective code generation of rectangularly tiled code, leading to further improvements in resource utilization. We demonstrate our techniques on a collection of affine benchmarks, reducing by 2x on average (up to 10x) the area used after High-Level Synthesis.
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memory partitioning for multidimensional arrays in High Level Synthesis
Design Automation Conference, 2013Co-Authors: Yuxin Wang, Peng Zhang, Chen Zhang, Jason CongAbstract:Memory partitioning is widely adopted to efficiently increase the memory bandwidth by using multiple memory banks and reducing data access conflict. Previous methods for memory partitioning mainly focused on one-dimensional arrays. As a consequence, designers must flatten a multidimensional array to fit those methodologies. In this work we propose an automatic memory partitioning scheme for multidimensional arrays based on linear transformation to provide High data throughput of on-chip memories for the loop pipelining in High-Level Synthesis. An optimal solution based on Ehrhart points counting is presented, and a heuristic solution based on memory padding is proposed to achieve a near optimal solution with a small logic overhead. Compared to the previous one-dimensional partitioning work, the experimental results show that our approach saves up to 21% of block RAMs, 19% in slices, and 46% in DSPs.
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improving High Level Synthesis optimization opportunity through polyhedral transformations
Field Programmable Gate Arrays, 2013Co-Authors: Wei Zuo, Yun Liang, Kyle Rupnow, Deming Chen, Jason CongAbstract:High Level Synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. It promises the performance and energy efficiency of hardware designs with a lower barrier to entry in design expertise, and shorter design time. State-of-the-art High Level Synthesis now includes a wide variety of powerful optimizations that implement efficient hardware. These optimizations can implement some of the most important features generally performed in manual designs including parallel hardware units, pipelining of execution both within a hardware unit and between units, and fine-grained data communication. We may generally classify the optimizations as those that optimize hardware implementation within a code block (intra-block) and those that optimize communication and pipelining between code blocks (inter-block). However, both optimizations are in practice difficult to apply. Real-world applications contain data-dependent blocks of code and communicate through complex data access patterns. Existing High Level Synthesis tools cannot apply these powerful optimizations unless the code is inherently compatible, severely limiting the optimization opportunity. In this paper we present an integrated framework to model and enable both intra- and inter-block optimizations. This integrated technique substantially improves the opportunity to use the powerful HLS optimizations that implement parallelism, pipelining, and fine-grained communication. Our polyhedral model-based technique systematically defines a set of data access patterns, identifies effective data access patterns, and performs the loop transformations to enable the intra- and inter-block optimizations. Our framework automatically explores transformation options, performs code transformations, and inserts the appropriate HLS directives to implement the HLS optimizations. Furthermore, our framework can automatically generate the optimized communication blocks for fine-grained communication between hardware blocks. Experimental evaluation demonstrates that we can achieve an average of 6.04X speedup over the High Level Synthesis solution without our transformations to enable intra- and inter-block optimizations.
Rajesh Gupta - One of the best experts on this subject based on the ideXlab platform.
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translation validation of High Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010Co-Authors: Sudipta Kundu, Sorin Lerner, Rajesh GuptaAbstract:The growing complexity of systems and their implementation into silicon encourages designers to look for ways to model designs at Higher Levels of abstraction and then incrementally build portions of these designs - automatically or manually - from these High-Level specifications. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. Therefore, checking if the implementation is a refinement or equivalent to its initial specification is of tremendous value. In this paper, we present an approach to automatically validate the implementation against its initial High-Level specification using insights from translation validation, automated theorem proving, and relational approaches to reasoning about programs. In our experiments, we first focus on concurrent systems modeled as communicating sequential processes and show that their refinements can be validated using our approach. Next, we have applied our validation approach to a realistic scenario - a parallelizing High-Level Synthesis framework called Spark. We present the details of our algorithm and experimental results.
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validating High Level Synthesis
Computer Aided Verification, 2008Co-Authors: Sudipta Kundu, Sorin Lerner, Rajesh GuptaAbstract:The growing design-productivity gap has made designers shift toward using High-Level languages like C, C++ and Java to do system-Level design. High-Level Synthesis (HLS) is the process of generating Register Transfer Level (RTL) design from these initial High-Level programs. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an approach to validate the result of HLS against the initial High-Level program using insights from translation validation, automated theorem proving and relational approaches to reasoning about programs. We have implemented our validating technique and have applied it to a Highly parallelizing HLS framework called SPARK . We present the details of our algorithm and experimental results.
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coordinated parallelizing compiler optimizations and High Level Synthesis
ACM Transactions on Design Automation of Electronic Systems, 2004Co-Authors: Sumit Gupta, Rajesh Gupta, Nikil Dutt, Alexandru NicolauAbstract:We present a High-Level Synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-Synthesis phase and during scheduling, with the objective of optimizing the results of Synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source Level preSynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-Level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing High-Level Synthesis in the SPARK framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer Level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool, validate the utility of our approach to the behavioral Synthesis of designs with complex control flows.
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using global code motions to improve the quality of results for High Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004Co-Authors: Sumit Gupta, Rajesh Gupta, Nikil Dutt, N Savoiu, Alexandru NicolauAbstract:The quality of Synthesis results for most High-Level Synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This leads to a need for High-Level and compiler transformations that overcome the effects of programming style on the quality of generated circuits. To address this issue, we have developed a set of speculative code-motion transformations that enable movement of operations through, beyond, and into conditionals with the objective of maximizing performance. We have implemented these code transformations, along with supporting code-motion techniques and variable renaming techniques, in a High-Level Synthesis research framework called Spark. Spark takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer Level VHDL. We present results for experiments on designs derived from three real-life multimedia and image processing applications, namely, the MPEG-1 and -2 and GNU image manipulation program applications. We find that the speculative-code motions lead to reductions between 36% and 59% in the number of states in the finite-state machine (controller complexity) and the cycles on the longest path (performance) compared with the case when only nonspeculative code motions are employed. Also, logic Synthesis results show fairly constant critical path lengths (clock period) and a marginal increase in area.
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speculation techniques for High Level Synthesis of control intensive designs
Design Automation Conference, 2001Co-Authors: Sumit Gupta, Rajesh Gupta, Nikil Dutt, Nick Savoiu, Sunwoo Kim, Alexandru NicolauAbstract:The quality of Synthesis results for most High Level Synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. In this paper, we explore the effectiveness of various types of code motions, such as moving operations across conditionals, out of conditionals (speculation) and into conditionals (reverse speculation), and how they can be effectively directed by heuristics so as to lead to improved Synthesis results in terms of fewer execution cycles and fewer number of states in the finite state machine controller. We also study the effects of the code motions on the area and latency of the final synthesized netlist. Based on speculative code motions, we present a novel way to perform early condition execution that leads to significant improvements in Highly control-intensive designs. Overall, reductions of up to 38 \% in execution cycles are obtained with all the code motions enabled.
Andrew Canis - One of the best experts on this subject based on the ideXlab platform.
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automating the design of processor accelerator embedded systems with legup High Level Synthesis
Embedded and Ubiquitous Computing, 2014Co-Authors: Blair Fort, Ruolong Lian, Nazanin Calagar, Andrew Canis, Jongsok Choi, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S CzajkowskiAbstract:LegUp [1] is an open-source High-Level Synthesis (HLS) tool that accepts a C program as input and automatically synthesizes it into a hybrid system. The hybrid system comprises an embedded processor and custom accelerators that realize user-designated compute-intensive parts of the program with improved throughput and energy efficiency. In this paper, we overview the LegUp framework and describe several recent developments: 1) support for an embedded ARM processor, as is available on Altera's recently released SoC FPGA, 2) HLS support for software parallelization schemes -- pthreads and OpenMP, 3) enhancements to LegUp's core HLS algorithms that raise the quality of the auto-generated hardware, and, 4) a preliminary debugging and verification framework providing C source-Level debugging of HLS hardware. Since its first release in 2011, LegUp has been downloaded over 1000 times by groups around the world, providing a powerful platform for new research in High-Level Synthesis algorithms and embedded systems design.
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from c to blokus duo with legup High Level Synthesis
Field-Programmable Technology, 2013Co-Authors: Jiu Cheng Cai, Ruolong Lian, Andrew Canis, Jongsok Choi, Mengyao Wang, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin CalagarAbstract:We apply High-Level Synthesis (HLS) to generate Blokus Duo game-playing hardware for the FPT 2013 Design Competition [3]. Our design, written in C, is synthesized using the LegUp open-source HLS tool to Verilog, then subsequently mapped using vendor tools to an Altera Cyclone IV FPGA on DE2 board. Our software implementation is designed to be amenable to High-Level Synthesis, and includes a custom stack implementation, uses only integer arithmetic, and employs the use of bitwise logical operations to improve overall computational performance. The underlying AI decision making is based on alpha-beta pruning [2]. The performance of our synthesizable solution is gauged by playing against the Pentobi [8] - a “known good” C++ software implementation.
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legup an open source High Level Synthesis tool for fpga based processor accelerator systems
ACM Transactions in Embedded Computing Systems, 2013Co-Authors: Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Stephen D Brown, Tomasz Czajkowski, Jason H AndersonAbstract:It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this article, we introduce a new High-Level Synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixed-sized multidimensional arrays, structs, global variables, and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial High-Level Synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software codesign space by varying the amount of a program that runs in software versus hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of High-Level Synthesis topics.
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From software to accelerators with LegUp High-Level Synthesis
2013 International Conference on Compilers Architecture and Synthesis for Embedded Systems CASES 2013, 2013Co-Authors: Andrew Canis, Jia Jun Qin, B Fort, Michael Gort, Ruolong Lian, Nazanin Calagar, Qijing Huang, Jongsok Choi, Mark Aldham, Tomasz CzajkowskiAbstract:Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source High-Level Synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
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impact of fpga architecture on resource sharing in High Level Synthesis
Field Programmable Gate Arrays, 2012Co-Authors: Stefan Hadjis, Andrew Canis, Jongsok Choi, Jason H Anderson, Stephen D Brown, Kevin Nam, Tomasz CzajkowskiAbstract:Resource sharing is a key area-reduction approach in High-Level Synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the High-Level circuit specification. We show that the utility of sharing depends on the underlying FPGA logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial FPGA families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs).