The Experts below are selected from a list of 45 Experts worldwide ranked by ideXlab platform

James W Tschanz - One of the best experts on this subject based on the ideXlab platform.

  • minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design, 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

  • ISLPED - Minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design (ISLPED), 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

Chiahsiang Chen - One of the best experts on this subject based on the ideXlab platform.

  • minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design, 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

  • ISLPED - Minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design (ISLPED), 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

Charles Augustine - One of the best experts on this subject based on the ideXlab platform.

  • minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design, 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

  • ISLPED - Minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design (ISLPED), 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

Keith Bowman - One of the best experts on this subject based on the ideXlab platform.

  • minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design, 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

  • ISLPED - Minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design (ISLPED), 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

Zhengya Zhang - One of the best experts on this subject based on the ideXlab platform.

  • minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design, 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.

  • ISLPED - Minimum supply voltage for sequential logic circuits in a 22nm technology
    International Symposium on Low Power Electronics and Design (ISLPED), 2013
    Co-Authors: Chiahsiang Chen, Keith Bowman, Charles Augustine, Zhengya Zhang, James W Tschanz
    Abstract:

    The minimum supply voltage (Vmin) is explored for sequential logic circuits by statistically simulating the impact of within-die process variations and gate-dielectric soft breakdown on data retention and Hold Time. As supply voltage (Vcc) scales, statistical circuit simulations demonstrate that Hold Time increases faster than circuit delay or cycle Time, consequently the required number of min-delay buffers increases. For this reason, a new Hold-Time Violation metric defines Vmin as the Vcc in which the Hold Time exceeds a target percentage of the cycle Time. Simulation results in a 22nm tri-gate CMOS technology indicate a data-retention Vmin of 0.61Vnorm and a Hold-Time Vmin of 0.73Vnorm, where Vnorm represents a normalized voltage for the process technology node. A key insight reveals that upsizing the first clock inverter in the sequential circuit reduces the Hold-Time Vmin by 18% and the overall Vmin by 16%.