The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Duncan Smith - One of the best experts on this subject based on the ideXlab platform.
-
Sequential Logic rectifications with approximate spfds
Design Automation and Test in Europe, 2009Co-Authors: Yushen Yang, Subarna Sinha, Andreas Veneris, Robert K Brayton, Duncan SmithAbstract:In the digital VLSI cycle, Logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on Sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFD-based Sequential Logic transformation methodology to tackle the problem with no sacrifice on performance. It first presents an efficient approach to construct approximate SPFDs (aSPFDs) for Sequential circuits. Then, it demonstrates an algorithm using aSPFDs to perform the desirable Sequential Logic transformations using both combinational and Sequential don't cares. Experimental results show the effectiveness and robustness of the approach.
-
DATE - Sequential Logic rectifications with approximate SPFDs
2009 Design Automation & Test in Europe Conference & Exhibition, 2009Co-Authors: Yushen Yang, Subarna Sinha, Andreas Veneris, Robert K Brayton, Duncan SmithAbstract:In the digital VLSI cycle, Logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on Sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFD-based Sequential Logic transformation methodology to tackle the problem with no sacrifice on performance. It first presents an efficient approach to construct approximate SPFDs (aSPFDs) for Sequential circuits. Then, it demonstrates an algorithm using aSPFDs to perform the desirable Sequential Logic transformations using both combinational and Sequential don't cares. Experimental results show the effectiveness and robustness of the approach.
Jin Xu - One of the best experts on this subject based on the ideXlab platform.
-
dna Sequential Logic gate using two ring dna
ACS Applied Materials & Interfaces, 2016Co-Authors: Cheng Zhang, Linjing Shen, Chao Liang, Yafei Dong, Jing Yang, Jin XuAbstract:Sequential DNA detection is a fundamental issue for elucidating the interactive relationships among complex gene systems. Here, a Sequential Logic DNA gate was achieved by utilizing the two-ring DNA structure, with the ability to recognize “before” and “after” triggering sequences of DNA signals. By taking advantage of a “loop-open” mechanism, separations of two-ring DNAs were controlled. Three triggering pathways with different Sequential DNA treatments were distinguished by comparing fluorescent outputs. Programmed nanoparticle arrangement guided by “interlocked” two-ring DNA was also constructed to demonstrate the achievement of designed nanostrucutres. Such Sequential Logic DNA operation may guide future molecular sensors to monitor more complex gene network in bioLogical systems.
P.d. Fisher - One of the best experts on this subject based on the ideXlab platform.
-
Efficient modelling and synthesis procedure of asynchronous Sequential Logic elements
IEE Proceedings - Computers and Digital Techniques, 1994Co-Authors: Jun-woo Kang, P.d. FisherAbstract:A model and procedure are developed for synthesising asynchronous Sequential Logic elements (ASLEs). This model represents the functional behaviour with a more compact form, and the procedure can synthesise them more efficiently than the traditional one. With the delineation of inputs as mode inputs,level inputs and edge inputs from the design specification, a set of equations can be generated which describes the Logic module's functional behaviour. The calculated states from these equations have bipartite adjacency relationships, which can easily be mapped onto an n-cube to obtain race-free state assignments. This procedure can also be applied for the synthesis of an asynchronous Sequential Logic circuit (ASLC) which has many data inputs and a small number of control inputs.
-
Fault effects in asynchronous Sequential Logic circuits
IEE Proceedings E (Computers and Digital Techniques), 1993Co-Authors: Ming-der Shieh, P.d. FisherAbstract:The paper demonstrates the effects of single stuck-at faults in Huffman-model asynchronous Sequential Logic circuits (ASLCs). The fault effects include equivalent-state redundant faults, invalid-state redundant faults and state oscillations. Equivalent-state redundant faults in ASLCs may be generated by violation of the fundamental mode constraint noncritical races or delays. On the other hand, invalid-state redundant faults are caused either by the existence of invalid states, or by improperly assigning the ‘don't-care’ terms. State oscillations are generally caused by the presence of critical races. Based on the fault effects, this paper presents a set of rules for synthe-sising oscillation-free ASLCs in the presence of faults. As far as synthesising testable ASLCs is concerned, the race-free UDC state assignment is much better than STT state assignment.
-
A scan design for asynchronous Sequential Logic circuits using SR-latches
Proceedings of 36th Midwest Symposium on Circuits and Systems, 1993Co-Authors: Ming-der Shieh, P.d. FisherAbstract:This paper presents a scan design for asynchronous Sequential Logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults. >
-
An efficient modeling and synthesis procedure of asynchronous Sequential Logic circuits
[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 1992Co-Authors: Jun-woo Kang, P.d. FisherAbstract:A model and procedure are developed for synthesizing asynchronous Sequential Logic circuits (ASLCs). This model represents the functional behavior with a more compact form and the procedure can synthesize them more efficiently than the traditional one. With the identification of edge inputs from the design specification, a set of equations can be generated which describes the functional behavior of the Logic module. The calculated states from these equations can easily be mapped onto an n-cube to obtain a race-free assignment. Further delineation of mode inputs and level inputs from data inputs facilitates the process of decomposing complex Logic functions into smaller ones which can be more easily synthesized. >
-
Automating the design of asynchronous Sequential Logic circuits
IEEE Journal of Solid-state Circuits, 1991Co-Authors: S.-f. Wu, P.d. FisherAbstract:The computer-aided design process described simplifies the task of designing asynchronous Sequential Logic circuits (ASLCs). It provides a highly structured, interactive approach for modeling Sequential Logic functions and for mapping these models into ASLC architectures and gate-level circuits. A design automation system that implements this process has been developed and tested. It contains five modules: (1) the behavioral descriptor, which maps the functional design specification into a primitive flow table; (2) the merger, which minimizes the number of states needed to implement the functional model; (3) the connector, which adds cycles and states, as needed, to avoid critical rates; (4) the assigner, which encodes the states and generates the state excitation table and output table; and (5) the equation generator, which eliminates static hazards and converts the state excitation table and output table into two-level, sum-of-product expressions for the state equations and output equations. This task-oriented system provides a convenient way to describe the functional behavior of Sequential Logic functions. It can reduce the design cycle time and improve the reliability of the overall ASLC design process and can also be used to facilitate the investigation of alternative ASLC architectures for the purpose of optimizing the performance of a specific Sequential Logic function. >
J H Patel - One of the best experts on this subject based on the ideXlab platform.
-
a graph traversal based framework for Sequential Logic implication with an application to c cycle redundancy identification
International Conference on VLSI Design, 2001Co-Authors: Jiankun Zhao, J A Newquist, J H PatelAbstract:This paper presents a new graph traversal based framework for Sequential Logic implication called GRAPH-SIMP. Due to the prohibitive time and space cost, few previous works target the discovery of Sequential indirect implications that span multiple time frames. By using an efficient graph data structure and incorporating a graph reduction step into the implication generation process, our approach provides an efficient support for Sequential implication. Sequential Logic implication has many useful applications, one of which is Sequentially redundant fault identification. We show that Sequential implications found by GRAPH SIMP allow us to find more Sequential redundancies than previously reported. Results of testing our implication algorithm against ISCAS89 circuits show that high implication coverage is essential to identifying redundant faults.
-
VLSI Design - A graph traversal based framework for Sequential Logic implication with an application to C-cycle redundancy identification
VLSI Design 2001. Fourteenth International Conference on VLSI Design, 2001Co-Authors: Jiankun Zhao, J A Newquist, J H PatelAbstract:This paper presents a new graph traversal based framework for Sequential Logic implication called GRAPH-SIMP. Due to the prohibitive time and space cost, few previous works target the discovery of Sequential indirect implications that span multiple time frames. By using an efficient graph data structure and incorporating a graph reduction step into the implication generation process, our approach provides an efficient support for Sequential implication. Sequential Logic implication has many useful applications, one of which is Sequentially redundant fault identification. We show that Sequential implications found by GRAPH SIMP allow us to find more Sequential redundancies than previously reported. Results of testing our implication algorithm against ISCAS89 circuits show that high implication coverage is essential to identifying redundant faults.
Shaojie Zhang - One of the best experts on this subject based on the ideXlab platform.
-
revisit Sequential Logic obfuscation attacks and defenses
International Symposium on Circuits and Systems, 2017Co-Authors: Travis Meade, Zheng Zhao, Shaojie ZhangAbstract:The urgent requests to protection integrated circuits (IC) and hardware intellectual properties (IP) have led to the development of various Logic obfuscation methods. While most existing solutions focus on the combinational Logic or Sequential Logic with full scan-chains, in this paper, we will revisit the security of Sequential Logic obfuscation within circuits where full scan-chains are not available or accessible. We will first introduce attack methods to compromise obfuscated Sequential circuits leveraging newly developed netlist analysis tools. We will then propose systematic solutions and provide guidelines in developing resilient Sequential Logic obfuscation schemes.
-
ISCAS - Revisit Sequential Logic obfuscation: Attacks and defenses
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017Co-Authors: Travis Meade, Zheng Zhao, Shaojie ZhangAbstract:The urgent requests to protection integrated circuits (IC) and hardware intellectual properties (IP) have led to the development of various Logic obfuscation methods. While most existing solutions focus on the combinational Logic or Sequential Logic with full scan-chains, in this paper, we will revisit the security of Sequential Logic obfuscation within circuits where full scan-chains are not available or accessible. We will first introduce attack methods to compromise obfuscated Sequential circuits leveraging newly developed netlist analysis tools. We will then propose systematic solutions and provide guidelines in developing resilient Sequential Logic obfuscation schemes.
