The Experts below are selected from a list of 12 Experts worldwide ranked by ideXlab platform

Valeria Bertacco - One of the best experts on this subject based on the ideXlab platform.

  • ForEVeR: A Complementary Formal and Runtime Verification Approach to Correct NoC Functionality
    2015
    Co-Authors: Ritesh Parikh, Valeria Bertacco
    Abstract:

    As silicon technology scales, modern processor and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs. As a side effect of complexity of these designs, ensuring their correctness has become increasingly problematic. Within these domains, Network-on-Chips (NoCs) are a de-facto choice to implement on-chip interconnect; their design is quickly becoming extremely complex in order to keep up with communication performance demands. As a result, design errors in the NoC may go undetected and escape into the final silicon. In this work, we propose ForEVeR, a solution that complements the use of formal methods and runtime verification to ensure functional correctness in NoCs. Formal verification, due to its scalability limitations, is used to verify smaller modules, such as Individual Router components. To deliver correctness guarantees for the complete network, we propose a network-level detection and recovery solution that monitors the traffic in the NoC and protects it against escaped functional bugs. To this end, ForEVeR augments the baseline NoC with a lightweight checker network that alerts destination nodes of incoming packets ahead of time. If a bug is detected, flagged by missed packet arrivals, our recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ForEVeR’s experimental evaluation shows that it can recover from NoC design errors at only 4.9 % area cost for an 8x8 mesh interconnect, over a time interva

  • formally enhanced runtime verification to ensure noc functional correctness
    International Symposium on Microarchitecture, 2011
    Co-Authors: Ritesh Parikh, Valeria Bertacco
    Abstract:

    As silicon technology scales, modern processors and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs, comprising several processor cores and IP components communicating via a network-on-chip (NoC). As a side-effect of this trend, ensuring their correctness has become increasingly problematic. In particular, the network-on-chip often includes complex features and components to support the required communication bandwidth among the nodes in the system. In this landscape, it is no wonder that design errors in the NoC may go undetected and escape into the final silicon, with potential detrimental impact on the overall system. In this work, we propose ForEVeR, a solution that complements the use of formal methods and runtime verification to ensure functional correctness in NoCs. Formal verification, due to its scalability limitations, is used to verify the smaller modules, such as Individual Router components. We complete the protection against escaped design errors with a runtime technique, a network-level error detection and recovery solution, which monitors the traffic in the NoC and protects it against escaped functional bugs that affect the communication paths in the network. To this end, ForEVeR augments the baseline NoC with a lightweight checker network that alerts destination nodes of incoming packets ahead of time. If a bug is detected, flagged by missed packet arrivals, a recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ForEVeR's experimental evaluation shows that it can recover from NoC design errors at only 4.8% area cost for an 8x8 mesh interconnect, with a recovery performance cost of less than 30K cycles per functional bug manifestation. Additionally, it incurs no performance overhead in the absence of errors.

Ritesh Parikh - One of the best experts on this subject based on the ideXlab platform.

  • ForEVeR: A Complementary Formal and Runtime Verification Approach to Correct NoC Functionality
    2015
    Co-Authors: Ritesh Parikh, Valeria Bertacco
    Abstract:

    As silicon technology scales, modern processor and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs. As a side effect of complexity of these designs, ensuring their correctness has become increasingly problematic. Within these domains, Network-on-Chips (NoCs) are a de-facto choice to implement on-chip interconnect; their design is quickly becoming extremely complex in order to keep up with communication performance demands. As a result, design errors in the NoC may go undetected and escape into the final silicon. In this work, we propose ForEVeR, a solution that complements the use of formal methods and runtime verification to ensure functional correctness in NoCs. Formal verification, due to its scalability limitations, is used to verify smaller modules, such as Individual Router components. To deliver correctness guarantees for the complete network, we propose a network-level detection and recovery solution that monitors the traffic in the NoC and protects it against escaped functional bugs. To this end, ForEVeR augments the baseline NoC with a lightweight checker network that alerts destination nodes of incoming packets ahead of time. If a bug is detected, flagged by missed packet arrivals, our recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ForEVeR’s experimental evaluation shows that it can recover from NoC design errors at only 4.9 % area cost for an 8x8 mesh interconnect, over a time interva

  • formally enhanced runtime verification to ensure noc functional correctness
    International Symposium on Microarchitecture, 2011
    Co-Authors: Ritesh Parikh, Valeria Bertacco
    Abstract:

    As silicon technology scales, modern processors and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs, comprising several processor cores and IP components communicating via a network-on-chip (NoC). As a side-effect of this trend, ensuring their correctness has become increasingly problematic. In particular, the network-on-chip often includes complex features and components to support the required communication bandwidth among the nodes in the system. In this landscape, it is no wonder that design errors in the NoC may go undetected and escape into the final silicon, with potential detrimental impact on the overall system. In this work, we propose ForEVeR, a solution that complements the use of formal methods and runtime verification to ensure functional correctness in NoCs. Formal verification, due to its scalability limitations, is used to verify the smaller modules, such as Individual Router components. We complete the protection against escaped design errors with a runtime technique, a network-level error detection and recovery solution, which monitors the traffic in the NoC and protects it against escaped functional bugs that affect the communication paths in the network. To this end, ForEVeR augments the baseline NoC with a lightweight checker network that alerts destination nodes of incoming packets ahead of time. If a bug is detected, flagged by missed packet arrivals, a recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ForEVeR's experimental evaluation shows that it can recover from NoC design errors at only 4.8% area cost for an 8x8 mesh interconnect, with a recovery performance cost of less than 30K cycles per functional bug manifestation. Additionally, it incurs no performance overhead in the absence of errors.

Fornaciari William - One of the best experts on this subject based on the ideXlab platform.

  • Monitor and Knob Techniques in Network-on-Chip Architectures
    'Springer Science and Business Media LLC', 2019
    Co-Authors: Zoni Davide, Englezakis Panayiotis, Chrysanthou Kypros, Canidio Andrea, Prodromou Andreas, Panteli Andreas, Nicopoulos Chrysostomos, Dimitrakopoulos Giorgos, Sazeides Yiannakis, Fornaciari William
    Abstract:

    This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and reliability issues pertaining to the NoC: (a) the BlackOut architecture is a fine-grained power-gating methodology targeting Individual Router buffers. Its goal is to minimize leakage power consumption, without adversely impacting the system performance; (b) the NoCAlert framework is a comprehensive on-line and real-time fault-detection and localization mechanism. Based on the concept of invariance checking, NoCAlert employs a group of lightweight micro-checker modules that collectively implement real-tim5e hardware assertions. Overall, the two solutions demonstrate the potential for ultrafast and low-cost monitor-and-knob mechanisms that can be applied to the NoC of multi-/many-core chips

  • BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip Routers
    'Elsevier BV', 2017
    Co-Authors: Zoni Davide, Englezakis Panayiotis, Canidio Andrea, Nicopoulos Chrysostomos, Fornaciari William, Sazeides Yiannakis
    Abstract:

    The Network-on-Chip (NoC) Router buffers play an instrumental role in the performance of both the interconnection fabric and the entire multi-/many-core system. Nevertheless, the buffers also constitute the major leakage power consumers in NoC implementations. Traditionally, they are designed to accommodate worst-case traffic scenarios, so they tend to remain idle, or under-utilized, for extended periods of time. The under-utilization of these valuable resources is exemplified when one profiles real application workloads; the generated traffic is bursty in nature, whereby high traffic periods are sporadic and infrequent, in general. The mitigation of the leakage power consumption of NoC buffers via power gating has been explored in the literature, both at coarse (Router-level) and fine (buffer-level) granularities. However, power gating at the Router granularity is suitable only for low and medium traffic conditions, where the Routers have enough opportunities to be powered down. Under high traffic, the sleeping potential rapidly diminishes. Moreover, disabling an entire Router greatly affects the NoC functionality and the network connectivity. This article presents BlackOut, a fine-grained power-gating methodology targeting Individual Router buffers. The goal is to minimize leakage power consumption, without adversely impacting the system performance. The proposed framework is agnostic of the routing algorithm and the network topology, and it is applicable to any Router micro-architecture. Evaluation results obtained using both synthetic traffic patterns and real applications in 64-core systems indicate energy savings of up to 70%, as compared to a baseline NoC, with a near-negligible performance overhead of around 2%. BlackOut is also shown to significantly outperformby 35%, on averagetwo current state-of-the-art power-gating solutions, in terms of energy savings. Not tailored to any topology, routing algorithm and NoC Router architecture.Router-to-Router communication. No need for custom, region-based/global networks.Effective at low, medium and high traffic. Other solutions are more restrictive.+35% energy saving, on average, against two state-of-the-art power-gating solutions.Negligible performance overhead (+2%) compared to the baseline architecture

Zoni Davide - One of the best experts on this subject based on the ideXlab platform.

  • Monitor and Knob Techniques in Network-on-Chip Architectures
    'Springer Science and Business Media LLC', 2019
    Co-Authors: Zoni Davide, Englezakis Panayiotis, Chrysanthou Kypros, Canidio Andrea, Prodromou Andreas, Panteli Andreas, Nicopoulos Chrysostomos, Dimitrakopoulos Giorgos, Sazeides Yiannakis, Fornaciari William
    Abstract:

    This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and reliability issues pertaining to the NoC: (a) the BlackOut architecture is a fine-grained power-gating methodology targeting Individual Router buffers. Its goal is to minimize leakage power consumption, without adversely impacting the system performance; (b) the NoCAlert framework is a comprehensive on-line and real-time fault-detection and localization mechanism. Based on the concept of invariance checking, NoCAlert employs a group of lightweight micro-checker modules that collectively implement real-tim5e hardware assertions. Overall, the two solutions demonstrate the potential for ultrafast and low-cost monitor-and-knob mechanisms that can be applied to the NoC of multi-/many-core chips

  • BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip Routers
    'Elsevier BV', 2017
    Co-Authors: Zoni Davide, Englezakis Panayiotis, Canidio Andrea, Nicopoulos Chrysostomos, Fornaciari William, Sazeides Yiannakis
    Abstract:

    The Network-on-Chip (NoC) Router buffers play an instrumental role in the performance of both the interconnection fabric and the entire multi-/many-core system. Nevertheless, the buffers also constitute the major leakage power consumers in NoC implementations. Traditionally, they are designed to accommodate worst-case traffic scenarios, so they tend to remain idle, or under-utilized, for extended periods of time. The under-utilization of these valuable resources is exemplified when one profiles real application workloads; the generated traffic is bursty in nature, whereby high traffic periods are sporadic and infrequent, in general. The mitigation of the leakage power consumption of NoC buffers via power gating has been explored in the literature, both at coarse (Router-level) and fine (buffer-level) granularities. However, power gating at the Router granularity is suitable only for low and medium traffic conditions, where the Routers have enough opportunities to be powered down. Under high traffic, the sleeping potential rapidly diminishes. Moreover, disabling an entire Router greatly affects the NoC functionality and the network connectivity. This article presents BlackOut, a fine-grained power-gating methodology targeting Individual Router buffers. The goal is to minimize leakage power consumption, without adversely impacting the system performance. The proposed framework is agnostic of the routing algorithm and the network topology, and it is applicable to any Router micro-architecture. Evaluation results obtained using both synthetic traffic patterns and real applications in 64-core systems indicate energy savings of up to 70%, as compared to a baseline NoC, with a near-negligible performance overhead of around 2%. BlackOut is also shown to significantly outperformby 35%, on averagetwo current state-of-the-art power-gating solutions, in terms of energy savings. Not tailored to any topology, routing algorithm and NoC Router architecture.Router-to-Router communication. No need for custom, region-based/global networks.Effective at low, medium and high traffic. Other solutions are more restrictive.+35% energy saving, on average, against two state-of-the-art power-gating solutions.Negligible performance overhead (+2%) compared to the baseline architecture

Englezakis Panayiotis - One of the best experts on this subject based on the ideXlab platform.

  • Monitor and Knob Techniques in Network-on-Chip Architectures
    'Springer Science and Business Media LLC', 2019
    Co-Authors: Zoni Davide, Englezakis Panayiotis, Chrysanthou Kypros, Canidio Andrea, Prodromou Andreas, Panteli Andreas, Nicopoulos Chrysostomos, Dimitrakopoulos Giorgos, Sazeides Yiannakis, Fornaciari William
    Abstract:

    This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and reliability issues pertaining to the NoC: (a) the BlackOut architecture is a fine-grained power-gating methodology targeting Individual Router buffers. Its goal is to minimize leakage power consumption, without adversely impacting the system performance; (b) the NoCAlert framework is a comprehensive on-line and real-time fault-detection and localization mechanism. Based on the concept of invariance checking, NoCAlert employs a group of lightweight micro-checker modules that collectively implement real-tim5e hardware assertions. Overall, the two solutions demonstrate the potential for ultrafast and low-cost monitor-and-knob mechanisms that can be applied to the NoC of multi-/many-core chips

  • BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip Routers
    'Elsevier BV', 2017
    Co-Authors: Zoni Davide, Englezakis Panayiotis, Canidio Andrea, Nicopoulos Chrysostomos, Fornaciari William, Sazeides Yiannakis
    Abstract:

    The Network-on-Chip (NoC) Router buffers play an instrumental role in the performance of both the interconnection fabric and the entire multi-/many-core system. Nevertheless, the buffers also constitute the major leakage power consumers in NoC implementations. Traditionally, they are designed to accommodate worst-case traffic scenarios, so they tend to remain idle, or under-utilized, for extended periods of time. The under-utilization of these valuable resources is exemplified when one profiles real application workloads; the generated traffic is bursty in nature, whereby high traffic periods are sporadic and infrequent, in general. The mitigation of the leakage power consumption of NoC buffers via power gating has been explored in the literature, both at coarse (Router-level) and fine (buffer-level) granularities. However, power gating at the Router granularity is suitable only for low and medium traffic conditions, where the Routers have enough opportunities to be powered down. Under high traffic, the sleeping potential rapidly diminishes. Moreover, disabling an entire Router greatly affects the NoC functionality and the network connectivity. This article presents BlackOut, a fine-grained power-gating methodology targeting Individual Router buffers. The goal is to minimize leakage power consumption, without adversely impacting the system performance. The proposed framework is agnostic of the routing algorithm and the network topology, and it is applicable to any Router micro-architecture. Evaluation results obtained using both synthetic traffic patterns and real applications in 64-core systems indicate energy savings of up to 70%, as compared to a baseline NoC, with a near-negligible performance overhead of around 2%. BlackOut is also shown to significantly outperformby 35%, on averagetwo current state-of-the-art power-gating solutions, in terms of energy savings. Not tailored to any topology, routing algorithm and NoC Router architecture.Router-to-Router communication. No need for custom, region-based/global networks.Effective at low, medium and high traffic. Other solutions are more restrictive.+35% energy saving, on average, against two state-of-the-art power-gating solutions.Negligible performance overhead (+2%) compared to the baseline architecture