The Experts below are selected from a list of 39 Experts worldwide ranked by ideXlab platform

Deog-kyoon Jeong - One of the best experts on this subject based on the ideXlab platform.

  • A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
    IEEE Journal of Solid-State Circuits, 2004
    Co-Authors: Jong Sang Choi, Moon Sang Hwang, Deog-kyoon Jeong
    Abstract:

    This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers Infinite Input Impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18- mu;m four-metal mixed-mode CMOS technology. The realized active area is 0.48 times;0.73 mm2. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

  • A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
    IEEE Journal of Solid-State Circuits, 2004
    Co-Authors: Jong Sang Choi, Moon Sang Hwang, Deog-kyoon Jeong
    Abstract:

    This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers Infinite Input Impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18-/spl mu/m four-metal mixed-mode CMOS technology. The realized active area is 0.48/spl times/0.73 mm/sup 2/. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

Jong Sang Choi - One of the best experts on this subject based on the ideXlab platform.

  • A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
    IEEE Journal of Solid-State Circuits, 2004
    Co-Authors: Jong Sang Choi, Moon Sang Hwang, Deog-kyoon Jeong
    Abstract:

    This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers Infinite Input Impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18- mu;m four-metal mixed-mode CMOS technology. The realized active area is 0.48 times;0.73 mm2. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

  • A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
    IEEE Journal of Solid-State Circuits, 2004
    Co-Authors: Jong Sang Choi, Moon Sang Hwang, Deog-kyoon Jeong
    Abstract:

    This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers Infinite Input Impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18-/spl mu/m four-metal mixed-mode CMOS technology. The realized active area is 0.48/spl times/0.73 mm/sup 2/. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

Moon Sang Hwang - One of the best experts on this subject based on the ideXlab platform.

  • A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
    IEEE Journal of Solid-State Circuits, 2004
    Co-Authors: Jong Sang Choi, Moon Sang Hwang, Deog-kyoon Jeong
    Abstract:

    This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers Infinite Input Impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18- mu;m four-metal mixed-mode CMOS technology. The realized active area is 0.48 times;0.73 mm2. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

  • A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
    IEEE Journal of Solid-State Circuits, 2004
    Co-Authors: Jong Sang Choi, Moon Sang Hwang, Deog-kyoon Jeong
    Abstract:

    This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers Infinite Input Impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18-/spl mu/m four-metal mixed-mode CMOS technology. The realized active area is 0.48/spl times/0.73 mm/sup 2/. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

N A Tantray - One of the best experts on this subject based on the ideXlab platform.

  • High Input Impedance All-Pass Circuit
    Iete Journal of Research, 1994
    Co-Authors: N A Shah, N A Tantray
    Abstract:

    A novel operational transconductance amplifier (OTA) based all-pass (AP) circuit exhibiting essentially Infinite Input Impedance and facilitating non-interactive electronic control of gain and phase without disturbing the AP condition is proposed. A large amount of gain is attainable from the circuit as the scale factor is a function of the product of transfer gain (gm) of OTA and grounded resistor which can be made voltage variable. The circuit can also be made digitally programmable by controlling the bias currents of OTAs with DAC.

Zhao Jianzhong - One of the best experts on this subject based on the ideXlab platform.

  • A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link
    Journal of Semiconductors, 2011
    Co-Authors: Zhou Yumei, Zhao Jianzhong
    Abstract:

    This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface, which is compliant with many serial communication specifications such as USB2.0, PCI-E2.0 and Rapid IO. The low and high frequency loops are merged to decrease the effect of delay between the two paths, in addition, the Infinite Input Impedance facilitates the cascade stages in order to improve the high frequency boosting gain. The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces, which brings as much as 25 dB loss. The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation. In addition, AC coupling is adopted to suppress the common Input from the forward stage. A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology. The actual area is 0.6 × 0.57 mm2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss. The overall power dissipation is approximately 23.4 mW.