The Experts below are selected from a list of 203181 Experts worldwide ranked by ideXlab platform
Michiel Steyaert - One of the best experts on this subject based on the ideXlab platform.
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a 1 25 gs s 7 b sar adc with 36 4 db sndr at 5 ghz using switch bootstrapping uspc dac and triple tail comparator in 28 nm cmos
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Athanasios Ramkaj, Michiel Steyaert, Maarten Strackx, Filip TavernierAbstract:This paper presents a 1.25-GS/s 7-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a low Input Frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz Input Frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the Input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.
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a 1 75 ghz 3 v dual modulus divide by 128 129 prescaler in 0 7 spl mu m cmos
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Jan Craninckx, Michiel SteyaertAbstract:A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-/spl mu/m CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum Input Frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum Input Frequency of 1.75 GHz.
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a 1 75 ghz 3 v dual modulus divide by 128 129 prescaler in 0 7 μm cmos
European Solid-State Circuits Conference, 1995Co-Authors: Jan Craninckx, Michiel SteyaertAbstract:A dual modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables to limit the high-speed section of the prescaler to only one divide-by-2 flipflop. That way a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum Input Frequency of the prescaler is up to 1.75 GHz, and the power consumption is 8 mA from a single 3-V power supply.
Navid R Zargari - One of the best experts on this subject based on the ideXlab platform.
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Space Vector Sequence Investigation and Synchronization Methods for Active Front-End Rectifiers in High-Power Current-Source Drives
IEEE Transactions on Industrial Electronics, 2008Co-Authors: Navid R ZargariAbstract:Space vector pulsewidth modulation (PWM) schemes for the active front end of a high-power drive normally produce low-order and suborder harmonics due to the low switching Frequency and the drifting of synchronization between the PWM waveform and the rectifier Input Frequency. To provide a synchronized PWM and achieve the best harmonic performance, different space vector sequences suitable for a current-source converter are investigated in this paper. Details on how to achieve the waveform symmetries with a minimum switching Frequency for each sequence are discussed. A thorough comparison of the harmonic performance of different space vector sequences is carried out. An optimum space vector modulation method by switching between two best sequences is proposed to achieve the best line-current total harmonic distortion with reduced switching losses. In addition, two synchronization methods, namely a PWM frame regulation method and a direct digital phase-locked loop synchronization method, are proposed. Both methods are equally effective in providing tight synchronization of the PWM waveform with the rectifier Input Frequency. The work has been verified in simulation and experiment.
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space vector sequence investigation and synchronization methods for pwm modulation of a high power current source rectifier
Power Electronics Specialists Conference, 2007Co-Authors: Navid R ZargariAbstract:Space vector PWM (SVPWM) schemes for high power current source rectifier (CSR) normally produce low order harmonics and sub-order harmonics due to the low switching Frequency and the drifting of synchronization between the PWM waveform and the CSR Input Frequency. To provide a synchronized PWM and achieve best harmonic performance, different space vector sequences suitable for a current source converter (CSC) are investigated in this paper. Details on how to achieve the waveform symmetries with minimum switching Frequency for each sequence are discussed. A thorough comparison of the harmonic performance of different space vector sequences is carried out. In addition, two synchronization methods, namely a PWM frame regulation method and a direct digital phase-locked loop (DPLL) synchronization method are proposed. Both methods are equally effective in providing tight synchronization of the PWM waveform with the CSR Input Frequency. The space vector sequence investigation and the developed synchronization methods are verified in simulation and experimentally using a 10 kVA GCT based CSR prototype.
M Tiebout - One of the best experts on this subject based on the ideXlab platform.
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a cmos direct injection locked oscillator topology as high Frequency low power Frequency divider
IEEE Journal of Solid-state Circuits, 2004Co-Authors: M TieboutAbstract:An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low Input capacitance, and highest Frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at Input Frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.
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a 480 spl mu w 2 ghz ultra low power dual modulus prescaler in 0 25 spl mu m standard cmos
International Symposium on Circuits and Systems, 2000Co-Authors: M TieboutAbstract:A dual modulus 128/129 prescaler is presented, consuming 480 /spl mu/W at a power supply voltage of 1.8 V and an Input Frequency of 2 GHz or 98 /spl mu/W at a power supply voltage of 1.5 V and an Input Frequency of 1 GHz. The prescaler was realized in Infineon 0.25 /spl mu/m standard CMOS process using single-phase clocked flipflops in the phase-switching prescaler architecture. The circuit was optimized for minimal power drain, maintaining a maximum operating Frequency of at least 2 GHz. Measured maximal Frequency of operation of the prescaler was 2.5 GHz. A co-integration of the prescaler with a voltage controlled LC-oscillator showed no detoriation of the -110 dBc/Hz phase-noise performance of the VCO at 100 kHz Frequency offset, thus proving the practical use of the circuit for synthesizers.
Karl F Bohringer - One of the best experts on this subject based on the ideXlab platform.
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converting vertical vibration of anisotropic ratchet conveyors into horizontal droplet motion
Langmuir, 2017Co-Authors: Yan Dong, Hal R. Holmes, Karl F BohringerAbstract:An anisotropic ratchet conveyor is an asymmetric, periodic, micropatterned surface that propels droplets when vibrated with a sinusoidal signal at certain frequencies and amplitudes. For each Input Frequency, there is a threshold amplitude beyond which the droplet starts to move. In this paper, we study the parameters that initiate droplet motion and the relationship between the Input Frequency and threshold amplitude among droplets with different volume, density, viscosity, and surface tension. Through this investigation we demonstrate how nondimensionalization reveals consistent behavior for droplets of different volumes. Finally, we propose a compact model that captures the essential features of the system to describe how a pure vertical vibration results in horizontal droplet motion. This model provides an intuitive understanding of the underlying physics and explains how the surface asymmetry is the key for lateral droplet motion.
Jan Craninckx - One of the best experts on this subject based on the ideXlab platform.
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a 1 75 ghz 3 v dual modulus divide by 128 129 prescaler in 0 7 spl mu m cmos
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Jan Craninckx, Michiel SteyaertAbstract:A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-/spl mu/m CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum Input Frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum Input Frequency of 1.75 GHz.
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a 1 75 ghz 3 v dual modulus divide by 128 129 prescaler in 0 7 μm cmos
European Solid-State Circuits Conference, 1995Co-Authors: Jan Craninckx, Michiel SteyaertAbstract:A dual modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables to limit the high-speed section of the prescaler to only one divide-by-2 flipflop. That way a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum Input Frequency of the prescaler is up to 1.75 GHz, and the power consumption is 8 mA from a single 3-V power supply.