The Experts below are selected from a list of 681 Experts worldwide ranked by ideXlab platform
Wei Meng Lim - One of the best experts on this subject based on the ideXlab platform.
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0 6mw 6 3 ghz 40nm cmos divide by 2 3 Prescaler using heterodyne phase locking technique
Electronics Letters, 2013Co-Authors: Wei Meng Lim, Kiat Seng YeoAbstract:A dual-modulus Prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus Prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.
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a 6 ghz dual modulus Prescaler using 180nm sige technology
International Symposium on Integrated Circuits, 2011Co-Authors: C Z Nan, Wei Meng Lim, Yang Liu, Kiat Seng YeoAbstract:A 6-GHz divide-by-3/4 Prescaler for fractional-N frequency synthesizers is presented in this paper. Optimization in the power consumption is carried out to ensure a high efficiency. Meanwhile, the critical cells, current-mode-logic (CML) building blocks, are optimized for high frequency and low power consumption. A prototype has been implemented in 180nm SiGe BiCMOS technology offered by Tower Jazz. The silicon area for the divide-by-3/4 Prescaler is only 40 μ m × 50 μ m. The maximum operating frequency can reach 6-GHz, with 7.92mW power consumption in 1.8V voltage supply.
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a 1 8 v 6 5 ghz low power wide band single phase clock cmos 2 3 Prescaler
International Midwest Symposium on Circuits and Systems, 2010Co-Authors: Vamshi M Krishna, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng LimAbstract:In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ Prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ Prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ Prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.
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design and analysis of ultra low power true single phase clock cmos 2 3 Prescaler
IEEE Transactions on Circuits and Systems I-regular Papers, 2010Co-Authors: M V Krishna, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng LimAbstract:In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency Prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 Prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 Prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus Prescaler implemented with this 2/3 Prescaler using a chartered 0.18 ?m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.
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design and optimization of the extended true single phase clock based Prescaler
IEEE Transactions on Microwave Theory and Techniques, 2006Co-Authors: Wei Meng Lim, Kiat Seng YeoAbstract:The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a Prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus Prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The Prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications
Kiat Seng Yeo - One of the best experts on this subject based on the ideXlab platform.
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0 6mw 6 3 ghz 40nm cmos divide by 2 3 Prescaler using heterodyne phase locking technique
Electronics Letters, 2013Co-Authors: Wei Meng Lim, Kiat Seng YeoAbstract:A dual-modulus Prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus Prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.
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a 6 ghz dual modulus Prescaler using 180nm sige technology
International Symposium on Integrated Circuits, 2011Co-Authors: C Z Nan, Wei Meng Lim, Yang Liu, Kiat Seng YeoAbstract:A 6-GHz divide-by-3/4 Prescaler for fractional-N frequency synthesizers is presented in this paper. Optimization in the power consumption is carried out to ensure a high efficiency. Meanwhile, the critical cells, current-mode-logic (CML) building blocks, are optimized for high frequency and low power consumption. A prototype has been implemented in 180nm SiGe BiCMOS technology offered by Tower Jazz. The silicon area for the divide-by-3/4 Prescaler is only 40 μ m × 50 μ m. The maximum operating frequency can reach 6-GHz, with 7.92mW power consumption in 1.8V voltage supply.
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a 1 8 v 6 5 ghz low power wide band single phase clock cmos 2 3 Prescaler
International Midwest Symposium on Circuits and Systems, 2010Co-Authors: Vamshi M Krishna, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng LimAbstract:In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ Prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ Prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ Prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.
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design and analysis of ultra low power true single phase clock cmos 2 3 Prescaler
IEEE Transactions on Circuits and Systems I-regular Papers, 2010Co-Authors: M V Krishna, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng LimAbstract:In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency Prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 Prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 Prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus Prescaler implemented with this 2/3 Prescaler using a chartered 0.18 ?m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.
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design and optimization of the extended true single phase clock based Prescaler
IEEE Transactions on Microwave Theory and Techniques, 2006Co-Authors: Wei Meng Lim, Kiat Seng YeoAbstract:The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a Prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus Prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The Prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications
W A M Van Noije - One of the best experts on this subject based on the ideXlab platform.
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a 4 1 ghz dual modulus Prescaler using the e tspc technique and double data throughput structures
International Symposium on Circuits and Systems, 2007Co-Authors: F P H De Miranda, Joao Adolfo Caldas Navarro, W A M Van NoijeAbstract:The design of a dual modulus Prescaler 32/33 in a 0.35mum CMOS technology is presented. In the circuit the technique called extended true single phase clock (E-TSPQ was applied. Additionally, some dedicated structures to double the data output rate were also employed. The Prescaler was implemented, tested and experimental results indicated that the circuit can reach up to 4.12 GHz with 4.93 mW of power consumption at 3.6 V power supply.
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a 4 ghz dual modulus divider by 32 33 Prescaler in 0 35 spl mu m cmos technology
Symposium on Integrated Circuits and Systems Design, 2004Co-Authors: F P H De Miranda, S J Navarro, W A M Van NoijeAbstract:The design of a dual modulus Prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The Prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the Prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.
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a 1 6 ghz dual modulus Prescaler using the extended true single phase clock cmos circuit technique e tspc
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Navarro J Soares, W A M Van NoijeAbstract:The implementation of a dual-modulus Prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC (E-TSPC), is presented. The E-TSPC consists of a set of composition rules for single-phase-clock circuits employing static, dynamic, latch, data-precharged, and NMOS-like CMOS blocks. The composition rules, as well as the CMOS blocks, are described and discussed. The experimental results of the complete dual-modulus Prescaler, implemented in a 0.8 /spl mu/m CMOS process, show a maximum 1.59 GHz operation rate at 5 V with 12.8 mW power consumption. They are compared with the results from other recent implementations showing that the proposed E-TSPC circuit can reach high speed with both smaller area and lower power consumption.
Masahiro Fujii - One of the best experts on this subject based on the ideXlab platform.
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an ultralow power consumption high speed gaas 256 258 dual modulus Prescaler ic
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Tadashi Maeda, S Wada, Masatoshi Tokushima, Masaoki Ishikawa, J Yamazaki, Masahiro FujiiAbstract:A GaAs divide-by-256/258 dual-modulus static Prescaler is described. The Prescaler has a pulse-swallow counter-type architecture and quasi-differential switch flip-flops as its basic circuit architecture. For the input buffer circuit, a circuit called a source-coupled push-pull circuit has been developed that can generate high-frequency complementary signals from a single-phase signal at a low supply voltage. This IC operates at up to 14.5 GHz with a power consumption of 22 mW. The power consumption is less than 1/50 of the previously reported Prescalers that can operate above 10 GHz.
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a 27 ghz 151 mw gaas 256 258 dual modulus Prescaler ic with 0 1 spl mu m double deck shaped dds gate e d hjfets
IEEE Gallium Arsenide Integrated Circuit Symposium, 1998Co-Authors: Shigeki Wada, Tadashi Maeda, Masatoshi Tokushima, Masaoki Ishikawa, Jin Yamazaki, Masahiro FujiiAbstract:We have developed 0.1-/spl mu/m double-deck-shaped (DDS) gate enhancement-mode (E) and depletion-mode (D) heterojunction (HJ) FET technology based upon an all-dry-etching process, which enables high current-gain cut-off frequencies (f/sub T/) in both E- and D-mode FETs above 100 GHz. We also report the first 256/258 dual-modulus Prescaler IC operating above 20 GHz with low power consumption. Obtained maximum input frequency for the Prescaler was 27 GHz with power consumption of 151 mW at a supply voltage of 1.2 V. This power consumption is about 1/50 of the value extrapolated from ones reported for Prescalers.
M V Krishna - One of the best experts on this subject based on the ideXlab platform.
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design and analysis of ultra low power true single phase clock cmos 2 3 Prescaler
IEEE Transactions on Circuits and Systems I-regular Papers, 2010Co-Authors: M V Krishna, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng LimAbstract:In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency Prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 Prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 Prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus Prescaler implemented with this 2/3 Prescaler using a chartered 0.18 ?m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.