The Experts below are selected from a list of 18 Experts worldwide ranked by ideXlab platform
B. Bushart - One of the best experts on this subject based on the ideXlab platform.
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Using FPGAs to Implement DSP Algorithms in Real Time for Gamma Spectroscopy Instruments
1999Co-Authors: B. BushartAbstract:Today's DSPs are capable of handling audio processing or even real time video processing; however, when the sample rate is equal to or exceeds the DSP Instruction Clock rate it becomes impossible to perform real time signal processing. The Savannah River Technology Center has developed a nearly all-digital radiation instrument that incorporates a single integer processor, as well as an FPGA.
Miao Ting - One of the best experts on this subject based on the ideXlab platform.
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The Design of 16-bit High Performance Microprocessor IP Softcore
China Integrated Circuit, 2007Co-Authors: Miao TingAbstract:Based on the analysis of the standard Intel8086 microprocessor, this paper introduces the design of one kind of 16-bit MPU IP softcore, which is reusable, high performance and Instruction set compatible with standard Intel 8086. From the partition of processor architecture to the design of Instruction set and various interior units, the design is elaborated in detail and software simulation and hardware validation are fulfilled. The performance of this processor obtains remarkable enhancement through the optimization in system architecture, such as compressing Instruction Clock Cycles, increasing Instruction Pre-Fetch Queue, improving Bus Interface Timing and reducing Effective Address Calculation Times and so on; Through including additional 80186 Instructions, this design implements fully software compatibility with standard 8086, 8088, 80186 and 80188 family of microprocessors.
H.g. Dietz - One of the best experts on this subject based on the ideXlab platform.
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RTCSA - Static scheduling of hard real-time code with Instruction-level timing accuracy
Proceedings of 3rd International Workshop on Real-Time Computing Systems and Applications, 1Co-Authors: T.m. Chung, H.g. DietzAbstract:In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each Instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on Instruction-level compiler code scheduling and timing analysis, and can ensure the timing of control operations to within a single Instruction Clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed.
T.m. Chung - One of the best experts on this subject based on the ideXlab platform.
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RTCSA - Static scheduling of hard real-time code with Instruction-level timing accuracy
Proceedings of 3rd International Workshop on Real-Time Computing Systems and Applications, 1Co-Authors: T.m. Chung, H.g. DietzAbstract:In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each Instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on Instruction-level compiler code scheduling and timing analysis, and can ensure the timing of control operations to within a single Instruction Clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed.
Massoud Pedram - One of the best experts on this subject based on the ideXlab platform.
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ICCD - Deterministic Clock gating to eliminate wasteful activity due to wrong-path Instructions in out-of-order superscalar processors
2009 IEEE International Conference on Computer Design, 2009Co-Authors: Nasir Mohyuddin, Kimish Patel, Massoud PedramAbstract:In this paper we present deterministic Clock gating schemes for various micro architectural blocks of a modern out-of-order superscalar processor. We propose to make use of 1) idle stages of the pipelined function units (FUs) and 2) wrong-path Instruction execution during branch mis-prediction, in order to Clock gate various stages of FUs. The baseline Pipelined Functional unit Clock Gating (PFCG), presented for evaluation purpose only, disables the Clock on idle stages and thus results in 13.93% chip-wide energy saving. Wrong-path Instruction Clock Gating (WPCG) detects wrong-path Instructions in the event of branch mis-prediction and prevents them from being issued to the FUs, and subsequently, disables the Clock of these FUs along with reducing the stress on register file and cache. Simulations demonstrate that more than 92% of all wrong-path Instructions can be detected and stopped from being executed. The WPCG architecture results in 16.26% chip-wide energy savings which is 2.33% more than that of the baseline PFCG scheme.