The Experts below are selected from a list of 39741 Experts worldwide ranked by ideXlab platform
Susan J Eggers - One of the best experts on this subject based on the ideXlab platform.
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converting thread level Parallelism to instruction level Parallelism via simultaneous multithreading
ACM Transactions on Computer Systems, 1997Co-Authors: Jack L Lo, Rebecca L Stamm, Dean M. Tullsen, Joel Emer, Henry M Levy, Susan J EggersAbstract:To achieve high performance, contemporary computer systems rely on two forms of Parallelism: Instruction-Level Parallelism (ILP) and thread-level Parallelism (TLP). Wide-issue super-scalar processors exploit ILP by executing multiple instructions from a single program in a single cycle. Multiprocessors (MP) exploit TLP by executing different threads in parallel on different processors. Unfortunately, both parallel processing styles statically partition processor resources, thus preventing them from adapting to dynamically changing levels of ILP and TLP in a program. With insufficient TLP, processors in an MP will be idle; with insufficient ILP, multiple-issue hardware on a superscalar is wasted. This article explores parallel processing on an alternative architecture, simultaneous multithreading (SMT), which allows multiple threads to complete for and share all of the processor's resources every cycle. The most compelling reason for running parallel applications on an SMT processor is its ability to use thread-level Parallelism and Instruction-Level Parallelism interchangeably. By permitting multiple threads to share the processor's functional units simultaneously, the processor can use both ILP and TLP to accommodate variations in Parallelism. When a program has only a single thread, all of the SMT processor's resources can be dedicated to that thread; when more TLP exists, this Parallelism can compensate for a lack of per-thread ILP. We examine two alternative on-chip parallel architectures for the next generation of processors. We compare SMT and small-scale, on-chip multiprocessors in their ability to exploit both ILP and TLP. First, we identify the hardware bottlenecks that prevent multiprocessors from effectively exploiting ILP. Then, we show that because of its dynamic resource sharing, SMT avoids these inefficiencies and benefits from being able to run more threads on a single processor. The use of TLP is especially advantageous when per-thread ILP is limited. The ease of adding additional thread contexts on an SMT (relative to adding additional processors on an MP) allows simultaneous multithreading to expose more Parallelism, further increasing functional unit utilization and attaining a 52% average speedup (versus a four-processor, single-chip multiprocessor with comparable execution resources). This study also addresses an often-cited concern regarding the use of thread-level Parallelism or multithreading: interference in the memory system and branch prediction hardware. We find the multiple threads cause interthread interference in the caches and place greater demands on the memory system, thus increasing average memory latencies. By exploiting threading-level Parallelism, however, SMT hides these additional latencies, so that they only have a small impact on total program performance. We also find that for parallel applications, the additional threads have minimal effects on branch prediction.
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PLDI - Improving balanced scheduling with compiler optimizations that increase Instruction-Level Parallelism
Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation - PLDI '95, 1995Co-Authors: Susan J EggersAbstract:Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory latency caused by cache hits and misses on non-blocking architectures. In contrast, balanced scheduling schedules instructions based on an estimate of the amount of Instruction-Level Parallelism in the program. By scheduling independent instructions behind loads based on what the program can provide, rather than what the implementation stipulates in the best case (i.e., a cache hit), balanced scheduling can hide variations in memory latencies more effectively. Since its success depends on the amount of Instruction-Level Parallelism in the code, balanced scheduling should perform even better when more Parallelism is available. In this study, we combine balanced scheduling with three compiler optimizations that increase Instruction-Level Parallelism: loop unrolling, trace scheduling and cache locality analysis. Using code generated for the DEC Alpha by the Multiflow compiler, we simulated a non-blocking processor architecture that closely models the Alpha 21164. Our results show that balanced scheduling benefits from all three optimizations, producing average speedups that range from 1.15 to 1.40, across the optimizations. More importantly, because of its ability to tolerate variations in load interlocks, it improves its advantage over traditional scheduling. Without the optimizations, balanced scheduled code is, on average, 1.05 times faster than that generated by a traditional scheduler; with them, its lead increases to 1.18.
Jarmo Takala - One of the best experts on this subject based on the ideXlab platform.
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impact of software bypassing on instruction level Parallelism and register file traffic
International Conference Workshop on Embedded Computer Systems: Architectures Modeling and Simulation, 2008Co-Authors: Vladimir Guzma, Pekka Jaaskelainen, Pertti Kellomaki, Jarmo TakalaAbstract:Software bypassing is a technique that allows programmer-controlled direct transfer of results of computations to the operands of data dependent operations, possibly removing the need to store some values in general purpose registers, while reducing the number of reads from the register file. Software bypassing also improves instruction level Parallelism by reducing the number of false dependencies between operations caused by the reuse of registers. In this work we show how software bypassing affects cycle count and reduces register file reads and writes. We analyze previous register file bypassing methods and compare them with our improved software bypassing implementation. In addition, we propose heuristics when not to apply software bypassing to retain scheduling freedom when selecting function units for operations. The results show that we get at best 27% improvement to cycle count, as well as up to 48% less register reads and 45% less register writes with the use of bypassing.
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SAMOS - Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic
Lecture Notes in Computer Science, 1Co-Authors: Vladimir Guzma, Pekka Jaaskelainen, Pertti Kellomaki, Jarmo TakalaAbstract:Software bypassing is a technique that allows programmer-controlled direct transfer of results of computations to the operands of data dependent operations, possibly removing the need to store some values in general purpose registers, while reducing the number of reads from the register file. Software bypassing also improves instruction level Parallelism by reducing the number of false dependencies between operations caused by the reuse of registers. In this work we show how software bypassing affects cycle count and reduces register file reads and writes. We analyze previous register file bypassing methods and compare them with our improved software bypassing implementation. In addition, we propose heuristics when not to apply software bypassing to retain scheduling freedom when selecting function units for operations. The results show that we get at best 27% improvement to cycle count, as well as up to 48% less register reads and 45% less register writes with the use of bypassing.
Marco Aldinucci - One of the best experts on this subject based on the ideXlab platform.
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Euro-Par - Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism
Lecture Notes in Computer Science, 2004Co-Authors: Kemal Ebcioglu, André Seznec, Wolfgang Karl, Marco AldinucciAbstract:Parallel architecture design and ILP architectures are important topics at the core of every parallel system, affecting the total system performance in fundamental ways. Instruction-Level Parallelism has for decades represented a foremost performance booster of leading edge computing systems. The present topic, Euro-par Topic 8, includes parallel computer architectures, processor architecture (microarchitecture as well as compilation), the impact of emerging microprocessor architectures on parallel computer architectures, innovative memory designs to hide and reduce the access latency, multi-threading, and the impact of emerging applications on parallel computer architecture design.
Saman Amarasinghe - One of the best experts on this subject based on the ideXlab platform.
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Software orchestration of instruction level Parallelism on tiled processor architectures
2005Co-Authors: Anant Agarwal, Saman Amarasinghe, Walter LeeAbstract:Projection from silicon technology is that while transistor budget will continue to blossom according to Moore's law, latency from global wires will severely limit the ability to scale centralized structures at high frequencies. A tiled processor architecture (TPA) eliminates long wires from its design by distributing its resources over a pipelined interconnect. By exposing the spatial distribution of these resources to the compiler, a TPA allows the compiler to optimize for locality, thus minimizing the distance that data needs to travel to reach the consuming computation. This thesis examines the compiler problem of exploiting instruction level Parallelism (ILP) on a TPA. It describes Rawcc, an ILP compiler for Raw, a fully distributed TPA. The thesis examines the implication of the resource distribution on the exploitation of ILP for each of the following resources: instructions, registers, control, data memory, and wires. It designs novel solutions for each one, and it describes the solutions within the integrated framework of a working compiler. Performance is evaluated on a cycle-accurate Raw simulator as well as on a 16-tile Raw chip. Results show that Rawcc can attain modest speedups for fine-grained applications, as well speedups that scale up to 64 tiles for applications with such Parallelism. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)
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space time scheduling of instruction level Parallelism on a raw machine
Architectural Support for Programming Languages and Operating Systems, 1998Co-Authors: Walter Lee, Rajeev Barua, Matthew I Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman AmarasingheAbstract:Increasing demand for both greater Parallelism and faster clocks dictate that future generation architectures will need to decentralize their resources and eliminate primitives that require single cycle global communication. A Raw microprocessor distributes all of its resources, including instruction streams, register files, memory ports, and ALUs, over a pipelined two-dimensional mesh interconnect, and exposes them fully to the compiler. Because communication in Raw machines is distributed, compiling for Instruction-Level Parallelism (ILP) requires both spatial instruction partitioning as well as traditional temporal instruction scheduling. In addition, the compiler must explicitly manage all communication through the interconnect, including the global synchronization required at branch points. This paper describes RAWCC, the compiler we have developed for compiling general-purpose sequential programs to the distributed Raw architecture. We present performance results that demonstrate that although Raw machines provide no mechanisms for global communication the Raw compiler can schedule to achieve speedups that scale with the number of available functional units.
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ASPLOS - Space-time scheduling of Instruction-Level Parallelism on a raw machine
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems - ASPLOS-VIII, 1998Co-Authors: Walter Lee, Rajeev Barua, Matthew I Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman AmarasingheAbstract:Increasing demand for both greater Parallelism and faster clocks dictate that future generation architectures will need to decentralize their resources and eliminate primitives that require single cycle global communication. A Raw microprocessor distributes all of its resources, including instruction streams, register files, memory ports, and ALUs, over a pipelined two-dimensional mesh interconnect, and exposes them fully to the compiler. Because communication in Raw machines is distributed, compiling for Instruction-Level Parallelism (ILP) requires both spatial instruction partitioning as well as traditional temporal instruction scheduling. In addition, the compiler must explicitly manage all communication through the interconnect, including the global synchronization required at branch points. This paper describes RAWCC, the compiler we have developed for compiling general-purpose sequential programs to the distributed Raw architecture. We present performance results that demonstrate that although Raw machines provide no mechanisms for global communication the Raw compiler can schedule to achieve speedups that scale with the number of available functional units.
Vladimir Guzma - One of the best experts on this subject based on the ideXlab platform.
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impact of software bypassing on instruction level Parallelism and register file traffic
International Conference Workshop on Embedded Computer Systems: Architectures Modeling and Simulation, 2008Co-Authors: Vladimir Guzma, Pekka Jaaskelainen, Pertti Kellomaki, Jarmo TakalaAbstract:Software bypassing is a technique that allows programmer-controlled direct transfer of results of computations to the operands of data dependent operations, possibly removing the need to store some values in general purpose registers, while reducing the number of reads from the register file. Software bypassing also improves instruction level Parallelism by reducing the number of false dependencies between operations caused by the reuse of registers. In this work we show how software bypassing affects cycle count and reduces register file reads and writes. We analyze previous register file bypassing methods and compare them with our improved software bypassing implementation. In addition, we propose heuristics when not to apply software bypassing to retain scheduling freedom when selecting function units for operations. The results show that we get at best 27% improvement to cycle count, as well as up to 48% less register reads and 45% less register writes with the use of bypassing.
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SAMOS - Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic
Lecture Notes in Computer Science, 1Co-Authors: Vladimir Guzma, Pekka Jaaskelainen, Pertti Kellomaki, Jarmo TakalaAbstract:Software bypassing is a technique that allows programmer-controlled direct transfer of results of computations to the operands of data dependent operations, possibly removing the need to store some values in general purpose registers, while reducing the number of reads from the register file. Software bypassing also improves instruction level Parallelism by reducing the number of false dependencies between operations caused by the reuse of registers. In this work we show how software bypassing affects cycle count and reduces register file reads and writes. We analyze previous register file bypassing methods and compare them with our improved software bypassing implementation. In addition, we propose heuristics when not to apply software bypassing to retain scheduling freedom when selecting function units for operations. The results show that we get at best 27% improvement to cycle count, as well as up to 48% less register reads and 45% less register writes with the use of bypassing.