The Experts below are selected from a list of 27798 Experts worldwide ranked by ideXlab platform
Wengfai Wong - One of the best experts on this subject based on the ideXlab platform.
-
A DVS-based Pipelined Reconfigurable Instruction Memory
2015Co-Authors: Tulika Mitra, Wengfai WongAbstract:Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruc-tion cache consumes a significant fraction of the total energy. One of the most popular methods to reduce the energy consumption is to shut down idle cache banks. However, we observe that operating idle cache banks at a reduced voltage/frequency level along with the active banks in a pipelined manner can potentially achieve even better energy savings. In this paper, we propose a novel DVS-based pipelined reconfigurable Instruction Memory hierarchy called PRIM. A canonical example of our proposed PRIM consists of four cache banks. Two of these cache banks can be configured at runtime to operate at lower voltage and frequency levels than that of the nor-mal cache. Instruction fetch throughput is maintained by pipelining the accesses to the low voltage banks. We developed a profile-driven compilation framework that analyzes applications and in-serts the appropriate cache reconfiguration points. Our experimen-tal results show that PRIM can significant reduce the energy con-sumption for popular embedded benchmarks with minimal perfor-mance overhead. We obtained 56.6 % and 45.1 % energy savings for aggressive and conservative VDD settings, respectively, at the expense of a 1.66 % performance overhead
-
DAC - A DVS-based pipelined reconfigurable Instruction Memory
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09, 2009Co-Authors: Tulika Mitra, Wengfai WongAbstract:Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the Instruction cache consumes a significant fraction of the total energy. One of the most popular methods to reduce the energy consumption is to shut down idle cache banks. However, we observe that operating idle cache banks at a reduced voltage/frequency level along with the active banks in a pipelined manner can potentially achieve even better energy savings. In this paper, we propose a novel DVS-based pipelined reconfigurable Instruction Memory hierarchy called PRIM. A canonical example of our proposed PRIM consists of four cache banks. Two of these cache banks can be configured at runtime to operate at lower voltage and frequency levels than that of the normal cache. Instruction fetch throughput is maintained by pipelining the accesses to the low voltage banks. We developed a profile-driven compilation framework that analyzes applications and inserts the appropriate cache reconfiguration points. Our experimental results show that PRIM can significant reduce the energy consumption for popular embedded benchmarks with minimal performance overhead. We obtained 56.6% and 45.1% energy savings for aggressive and conservative VDD settings, respectively, at the expense of a 1.66% performance overhead.
-
DATE - DRIM: a low power dynamically reconfigurable Instruction Memory hierarchy for embedded systems
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Wengfai Wong, Hock-beng LimAbstract:Power consumption is of crucial importance to embedded systems. In such systems, the Instruction Memory hierarchy consumes a large portion of the total energy consumption. A well designed Instruction Memory hierarchy can greatly decrease the energy consumption and increase performance. The performance of the Instruction Memory hierarchy is largely determined by the specific application. Different applications achieve better energy-performance with different configurations of the Instruction Memory hierarchy. Moreover, applications often exhibit different phases during execution, each exacting different demands on the processor and in particular the Instruction Memory hierarchy. For a given hardware resource budget, an even better energy-performance may be achievable if the Memory hierarchy can be reconfigured before each of these phases. In this paper, we propose a new dynamically reconfigurable Instruction Memory hierarchy to take advantage of these two characteristics so as to achieve significant energy-performance improvement. Our proposed Instruction Memory hierarchy, which we called DRIM, consists of four banks of on-chip Instruction buffers. Each of these can be configured to function as a cache or as a scratchpad Memory (SPM) according to the needs of an application and its execution phases. Our experimental results using six benchmarks from the MediaBench and the MiBench suites show that DRIM can achieve significant energy reduction.
-
a reconfigurable Instruction Memory hierarchy for embedded systems
Field-Programmable Logic and Applications, 2005Co-Authors: Hock Lim, Wengfai WongAbstract:The performance of the Instruction Memory hierarchy is of crucial importance in embedded systems. In this paper, we propose a reconfigurable Instruction Memory hierarchy for embedded systems whose architectural parameters can be customized for specific applications. The proposed Instruction Memory hierarchy consists of an Instruction cache and a scratchpad Memory (SPM). We propose an algorithm to manage this Instruction Memory hierarchy and optimize its performance. Given a fixed amount of reconfigurable on-chip storage resources and an application, our algorithm determines the sizes of the SPM and the Instruction cache to best suit the application. It analyzes the application, partitions the available storage resources into SPM and cache, and assigns Instructions to them. Our algorithm aims to reduce the Instruction fetch miss rate, improve the system performance, and reduce the energy consumption. We have implemented this reconfigurable Instruction Memory hierarchy on the Altera Nios II FPGA platform. Our experimental results using five benchmarks from the MediaBench and the MiBench suites show that our proposed architecture provides significant performance improvements and energy reduction.
-
FPL - A reconfigurable Instruction Memory hierarchy for embedded systems
International Conference on Field Programmable Logic and Applications 2005., 1Co-Authors: Hock Lim, Wengfai WongAbstract:The performance of the Instruction Memory hierarchy is of crucial importance in embedded systems. In this paper, we propose a reconfigurable Instruction Memory hierarchy for embedded systems whose architectural parameters can be customized for specific applications. The proposed Instruction Memory hierarchy consists of an Instruction cache and a scratchpad Memory (SPM). We propose an algorithm to manage this Instruction Memory hierarchy and optimize its performance. Given a fixed amount of reconfigurable on-chip storage resources and an application, our algorithm determines the sizes of the SPM and the Instruction cache to best suit the application. It analyzes the application, partitions the available storage resources into SPM and cache, and assigns Instructions to them. Our algorithm aims to reduce the Instruction fetch miss rate, improve the system performance, and reduce the energy consumption. We have implemented this reconfigurable Instruction Memory hierarchy on the Altera Nios II FPGA platform. Our experimental results using five benchmarks from the MediaBench and the MiBench suites show that our proposed architecture provides significant performance improvements and energy reduction.
Francky Catthoor - One of the best experts on this subject based on the ideXlab platform.
-
Design exploration of a NVM based hybrid Instruction Memory organization for embedded platforms
Design Automation for Embedded Systems, 2013Co-Authors: Manu Perumkunnil Komalan, Antonio Artes, José Ignacio Gómez Pérez, Christian Tenllado, José Miguel Montañana, José Francisco Tirado Fernández, Francky CatthoorAbstract:Non volatile Memory (NVM) technologies are being explored extensively to replace conventional SRAM based memories. The main focus of this paper is the exploration of a NVM based Instruction Memory in low power embedded systems for wireless or multimedia target applications. A SRAM based traditional Instruction Memory organization suitable for the target applications is taken as the base. Different Resistive RAM (ReRAM) based organizations are then designed as alternatives keeping in mind their limitations (write process related), and energy and performance trade-offs. The NVM array design is explored and optimized based on energy and performance trade-offs. Dynamic Instruction mapping and architectural design changes are utilized to minimize ReRAM limitations and maximize its positive contributions. Energy and performance values are obtained by extension of CACTI models, Spice and VHDL simulations. The best ReRAM based hybrid Instruction Memory organization that utilizes our proposed methodology showed significantly lower energy consumption (up-to 82.07 % read energy reduction) even in case of 0 % performance penalty.
-
Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems
Journal of Signal Processing Systems, 2013Co-Authors: Antonio Artes, José L. Ayala, Praveen Raghavan, Robert Fasthuber, Francky CatthoorAbstract:The use of distributed loop buffer architectures with incompatible loop-nest organisations allows the execution of incompatible loops in parallel with minimal hardware overhead. Due to this fact, the utilisation of these distributed and scalable architectures in embedded systems is a promising option to improve the energy efficiency of the Instruction Memory organisations that exist in these systems. This paper proposes and analyses non-overlapping and complementary implementation options for distinct partitions of the design space that is related to distributed loop buffer architectures. The high-level trade-off analysis of the proposed implementations is crucial to present the correct process design that an embedded systems designer has to follow in order to have an efficient distributed loop buffer architecture for a certain application. Results show that, with an increase of about 6.5 % in the energy consumption of the control logic that exists in the Instruction Memory organisation, the overall energy consumption of the Instruction Memory organisation can be reduced by 6 % to 22 %, when distributed loop buffer architectures with incompatible loop-nest organisations are used instead of clustered loop buffer architectures with shared loop-nest organisations architectures.
-
VLSI-SoC - Energy impact in the design space exploration of loop buffer schemes in embedded systems
2013 IFIP IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 2013Co-Authors: Antonio Artes, José L. Ayala, Praveen Raghavan, Robert Fasthuber, Francky CatthoorAbstract:The reduction of the energy consumption in the domain of the embedded systems is becoming the most important design goal due to the increasing use of battery powered consumer devices. Previous research has pointed out the Instruction Memory organisation as one of the major sources of energy consumption of the embedded systems. Due to this fact, the introduction of any enhancement in this component of the system becomes crucial in order to decrease this energy bottleneck. The purpose of this paper is to present a highlevel energy analysis of the loop buffer schemes that exist in the embedded systems. The crucial energy analysis that is presented in this paper not only proposes a method to evaluate different loop buffer schemes for a certain application, but also guides embedded systems designers to make the correct decision in the trade-offs that exist between the energy budget, the required performance, and the area cost of the embedded system. Experimental results used in this analysis show that, the search of energy savings (up to 76%) has to take into account the performance penalty, the area cost, and the impact of the implementation technology in order to choose the most suitable enhancement that has to be introduced in the Instruction Memory organisation from the point of view of the energy consumption.
-
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
Journal of Signal Processing Systems, 2013Co-Authors: Antonio Artes, José L. Ayala, Jos Huisken, Francky CatthoorAbstract:Instruction Memory organisations have been pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterised by restrictive resources and a low-energy budget, any enhancement that is introduced into this component of the system will allow embedded designers not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the whole system. The work that is presented in this paper provides a synthesis on the low-energy techniques that are used in Instruction Memory organisations, outlining their comparative advantages, drawbacks, and trade-offs. Apart from giving the reader a first grasp on the fundamental characteristics and design constraints of various types of Instruction Memory organisations, the architectural classification that is presented in this paper has the advantage of clearly exhibiting lesser explored techniques, and hence providing hints for future research on Instructions Memory organisations that are used in embedded systems.
-
Power Impact of Loop Buffer Schemes for Biomedical Wireless Sensor Nodes
Sensors (Basel Switzerland), 2012Co-Authors: Antonio Artes, José L. Ayala, Francky CatthoorAbstract:Instruction Memory organisations are pointed out as one of the major sources of energy consumption in embedded systems. As these systems are characterised by restrictive resources and a low-energy budget, any enhancement in this component allows not only to decrease the energy consumption but also to have a better distribution of the energy budget throughout the system. Loop buffering is an effective scheme to reduce energy consumption in Instruction Memory organisations. In this paper, the loop buffer concept is applied in real-life embedded applications that are widely used in biomedical Wireless Sensor Nodes, to show which scheme of loop buffer is more suitable for applications with certain behaviour. Post-layout simulations demonstrate that a trade-off exists between the complexity of the loop buffer architecture and the energy savings of utilising it. Therefore, the use of loop buffer architectures in order to optimise the Instruction Memory organisation from the energy efficiency point of view should be evaluated carefully, taking into account two factors: (1) the percentage of the execution time of the application that is related to the execution of the loops, and (2) the distribution of the execution time percentage over each one of the loops that form the application.
Hock Lim - One of the best experts on this subject based on the ideXlab platform.
-
a reconfigurable Instruction Memory hierarchy for embedded systems
Field-Programmable Logic and Applications, 2005Co-Authors: Hock Lim, Wengfai WongAbstract:The performance of the Instruction Memory hierarchy is of crucial importance in embedded systems. In this paper, we propose a reconfigurable Instruction Memory hierarchy for embedded systems whose architectural parameters can be customized for specific applications. The proposed Instruction Memory hierarchy consists of an Instruction cache and a scratchpad Memory (SPM). We propose an algorithm to manage this Instruction Memory hierarchy and optimize its performance. Given a fixed amount of reconfigurable on-chip storage resources and an application, our algorithm determines the sizes of the SPM and the Instruction cache to best suit the application. It analyzes the application, partitions the available storage resources into SPM and cache, and assigns Instructions to them. Our algorithm aims to reduce the Instruction fetch miss rate, improve the system performance, and reduce the energy consumption. We have implemented this reconfigurable Instruction Memory hierarchy on the Altera Nios II FPGA platform. Our experimental results using five benchmarks from the MediaBench and the MiBench suites show that our proposed architecture provides significant performance improvements and energy reduction.
-
FPL - A reconfigurable Instruction Memory hierarchy for embedded systems
International Conference on Field Programmable Logic and Applications 2005., 1Co-Authors: Hock Lim, Wengfai WongAbstract:The performance of the Instruction Memory hierarchy is of crucial importance in embedded systems. In this paper, we propose a reconfigurable Instruction Memory hierarchy for embedded systems whose architectural parameters can be customized for specific applications. The proposed Instruction Memory hierarchy consists of an Instruction cache and a scratchpad Memory (SPM). We propose an algorithm to manage this Instruction Memory hierarchy and optimize its performance. Given a fixed amount of reconfigurable on-chip storage resources and an application, our algorithm determines the sizes of the SPM and the Instruction cache to best suit the application. It analyzes the application, partitions the available storage resources into SPM and cache, and assigns Instructions to them. Our algorithm aims to reduce the Instruction fetch miss rate, improve the system performance, and reduce the energy consumption. We have implemented this reconfigurable Instruction Memory hierarchy on the Altera Nios II FPGA platform. Our experimental results using five benchmarks from the MediaBench and the MiBench suites show that our proposed architecture provides significant performance improvements and energy reduction.
Geert Deconinck - One of the best experts on this subject based on the ideXlab platform.
-
Impact of ILP-improving code transformations on loop buffer energy
2007Co-Authors: T. Van Der Aa, Francky Catthoor, Murali Jayapala, Henk Corporaal, Geert DeconinckAbstract:For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the Instruction Memory of embedded processors. In particular, software controlled clustered loop buffers are very energy efficient. However code transformations needed in VLIW compilers to reach a higher ILP potentially may have a large negative influence on the energy consumed in the Instruction memories (including the loop buffer). This paper will show that such code transformations can also have a positive impact on the Instruction Memory energy of processors, if the transformations are steered taking into account the presence of the software controlled clustered loop buffer. We will propose guidelines to steer the code transformations and show that these guidlines should be differently applied in a system with clustered loop buffer than in a system with only a normal Instruction cache. Results are presented for a mix of three important ILP code transformations: software-pipelining, if-conversion and loop unrolling. Results show an energy reduction between 15% and 25% and a delay reduction between 60% and 75% for an MPEG-2 Video Encoder benchmark.
-
Efficient Architecture Exploration of a Clustered Loop Buffer
2006Co-Authors: Murali Jayapala, Francky Catthoor, Henk Corporaal, Geert DeconinckAbstract:For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the Instruction Memory of embedded processors. In particular, software controlled clustered loop buffers are very energy efficient. This paper presents an exploration methodology to find the optimal clustering configuration of the loop buffer for a specific application. Three different methods are presented that provide a trade-off between exploration time and quality of the solution. Results for the MediaBench benchmark suite show an energy reduction in the complete Instruction Memory hierarchy of 10%, with peaks of 50% for some applications with respect to a nonclustered centralized loop buffer.
-
SiPS - Instruction Transfer And Storage Exploration for Low Energy VLIWs
2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 2006Co-Authors: Murali Jayapala, Francky Catthoor, Henk Corporaal, Geert DeconinckAbstract:For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the Instruction Memory of embedded processors. In particular, software controlled clustered loop buffers are potentially very energy efficient. However current compilers for VLIW do not fully exploit the potentials offered by such a clustered organization. This paper presents ITSE, Instruction Transfer and Storage Exploration, a methodology to minimize the Instruction Memory energy using a software controlled clustered loop buffer as a basis. Results for the MediaBench application suite show 61% reduction (on average) in energy in the Instruction Memory hierarchy as compared to traditional, existing non-clustered approaches to the loop buffer without compromising performance.
-
PATMOS - Instruction buffering exploration for low energy embedded processors
2005Co-Authors: Murali Jayapala, F Barat, Geert Deconinck, Henk Corporaal, Rudy Lauwereins, Francky CatthoorAbstract:For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the Instruction Memory of embedded processors. Especially software controlled loop buffers are energy efficient. However current compilers do not fully take advantage of the possibilities of such loop buffers. This paper presents an algorithm to explore for an application or a set of applications what is the optimal loop buffer configuration and the optimal way to use this configuration. Results for the MediaBench application suite show an additional 35% reduction (on average) in energy in the Instruction Memory hierarchy as compared to traditional approaches to the loop buffer without any performance implications.
-
ESTImedia - Combining data and Instruction Memory energy optimizations for embedded applications
3rd Workshop on Embedded Systems for Real-Time Multimedia 2005., 2005Co-Authors: Francky Catthoor, Henk Corporaal, Geert DeconinckAbstract:This paper studies the overhead of data Memory optimizations on the Instruction memories in embedded processors. First, it is shown that this overhead is significant, but methods exist to alleviate it. For every data optimization step causing overhead, there exists an appropriate countermeasure such that both Instruction and data energy is kept low. Results on two driver applications show that although the overhead in both energy and performance can reach up to 250%, the countermeasures reduce this, such that the final result has up to four times less energy consumption and up seven times better performance compared to the original implementation.
Murali Jayapala - One of the best experts on this subject based on the ideXlab platform.
-
Multi-threading in Uni-threaded Processor
Ultra-Low Energy Domain-Specific Instruction-Set Processors, 2010Co-Authors: Francky Catthoor, Murali Jayapala, Praveen Raghavan, Andy Lambrechts, Angeliki Kritikakou, Javed AbsarAbstract:This chapter introduces the concept of executing multiple incompatible loops in parallel and thereby enabling multi-threading in an efficient way in a VLIW processor. The proposed multi-threading is enabled by the use of a distributed Instruction Memory organization with a minimal hardware overhead. This forms one of the core contributions of this book. It also shows how the proposed Instruction Memory hierarchy extension can both improve performance as well as reduce the energy consumption compared to state-of-the-art simultaneous multi-threaded (SMT) architectures over various DSP benchmarks. The chapter also shows that the proposed architecture can be compiled for.
-
Clustered L0 (Loop) Buffer Organization and Combination with Data Clusters
Ultra-Low Energy Domain-Specific Instruction-Set Processors, 2010Co-Authors: Francky Catthoor, Murali Jayapala, Praveen Raghavan, Andy Lambrechts, Angeliki Kritikakou, Javed AbsarAbstract:A distributed L0 buffer organization is an energy-efficient template for augmenting the Instruction Memory organization at the lowest level of the Instruction Memory hierarchy. In particular, functional units in the datapath are grouped into logical units called L0 clusters. Each L0 cluster obtains an associated L0 buffer which stores the Instructions (coded operations) corresponding to the functional units in that cluster. Also, a local controller in each L0 cluster is responsible for indexing into and progressing through the L0 buffers. In this chapter, that control is however limited to conditions and the loop nest still has to be fully compatible between the L0 buffers. That limitation will be relieved in the next chapter. One of the principal energy-improving aspects in this book is the architecture concept embedded in such a distributed L0 buffer organization. Generating application-specific L0 clusters and compiling for L0 clusters are ways to exploit that distributed organization. In this chapter the repertoire of the organization is described and the key architectural parameters are introduced.
-
Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures
IEEE Transactions on Computers, 2009Co-Authors: Praveen Raghavan, F. Catthoor, Murali Jayapala, Andy Lambrechts, Diederik VerkestAbstract:Reduced energy consumption is one of the most important design goals for embedded application domains like wireless communication, multimedia and biomedical applications. The Instruction Memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the Instruction Memory to reduce energy consumption and improve performance. The proposed distributed Instruction Memory organization requires minimal hardware overhead and supports the execution of multiple incompatible loops in parallel in a uni-processor system. We present different methods to implement the loop controller architecture, compare them, and show that distributing the Instruction Memory helps to reduce the interconnect cost as well. This architecture enhancement can reduce the energy consumed in the Instruction Memory hierarchy by 59% and improve the performance by 22% compared to hardware based enhanced SMT based architectures.
-
Impact of ILP-improving code transformations on loop buffer energy
2007Co-Authors: T. Van Der Aa, Francky Catthoor, Murali Jayapala, Henk Corporaal, Geert DeconinckAbstract:For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the Instruction Memory of embedded processors. In particular, software controlled clustered loop buffers are very energy efficient. However code transformations needed in VLIW compilers to reach a higher ILP potentially may have a large negative influence on the energy consumed in the Instruction memories (including the loop buffer). This paper will show that such code transformations can also have a positive impact on the Instruction Memory energy of processors, if the transformations are steered taking into account the presence of the software controlled clustered loop buffer. We will propose guidelines to steer the code transformations and show that these guidlines should be differently applied in a system with clustered loop buffer than in a system with only a normal Instruction cache. Results are presented for a mix of three important ILP code transformations: software-pipelining, if-conversion and loop unrolling. Results show an energy reduction between 15% and 25% and a delay reduction between 60% and 75% for an MPEG-2 Video Encoder benchmark.
-
Efficient Architecture Exploration of a Clustered Loop Buffer
2006Co-Authors: Murali Jayapala, Francky Catthoor, Henk Corporaal, Geert DeconinckAbstract:For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the Instruction Memory of embedded processors. In particular, software controlled clustered loop buffers are very energy efficient. This paper presents an exploration methodology to find the optimal clustering configuration of the loop buffer for a specific application. Three different methods are presented that provide a trade-off between exploration time and quality of the solution. Results for the MediaBench benchmark suite show an energy reduction in the complete Instruction Memory hierarchy of 10%, with peaks of 50% for some applications with respect to a nonclustered centralized loop buffer.