The Experts below are selected from a list of 42324 Experts worldwide ranked by ideXlab platform

Yongkook Kim - One of the best experts on this subject based on the ideXlab platform.

  • concurrent error detection schemes for fault based side channel cryptanalysis of symmetric block ciphers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or Performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, Performance Penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

  • fault based side channel cryptanalysis tolerant rijndael symmetric block cipher architecture
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2001
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or Performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, Performance Penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.

  • concurrent error detection of fault based side channel cryptanalysis of 128 bit symmetric block ciphers
    Design Automation Conference, 2001
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or Performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, Performance Penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.

Ramesh Karri - One of the best experts on this subject based on the ideXlab platform.

  • concurrent error detection schemes for fault based side channel cryptanalysis of symmetric block ciphers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or Performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, Performance Penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

  • fault based side channel cryptanalysis tolerant rijndael symmetric block cipher architecture
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2001
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or Performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, Performance Penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.

  • concurrent error detection of fault based side channel cryptanalysis of 128 bit symmetric block ciphers
    Design Automation Conference, 2001
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or Performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, Performance Penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.

Piyush Mishra - One of the best experts on this subject based on the ideXlab platform.

  • concurrent error detection schemes for fault based side channel cryptanalysis of symmetric block ciphers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or Performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, Performance Penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

  • fault based side channel cryptanalysis tolerant rijndael symmetric block cipher architecture
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2001
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or Performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, Performance Penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.

  • concurrent error detection of fault based side channel cryptanalysis of 128 bit symmetric block ciphers
    Design Automation Conference, 2001
    Co-Authors: Ramesh Karri, Piyush Mishra, Yongkook Kim
    Abstract:

    Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or Performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, Performance Penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.

Massoud Pedram - One of the best experts on this subject based on the ideXlab platform.

  • tei noc optimizing ultralow power nocs exploiting the temperature effect inversion
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
    Co-Authors: Kyuseung Han, Woojoo Lee, Jaejin Lee, Jinho Lee, Massoud Pedram
    Abstract:

    The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern of system-on-chip designers. Ultralow power (ULP) very large-scale integration circuits have been receiving considerable interest from both academia and industry as the best-suited techniques for IoT devices, which can take full advantage of power-saving that voltage scaling potentially achieves. Consequently, research on ULP designs has begun to yield tangible outcomes, namely ULP circuits. However, little attention has been paid to ULP network-on-chip (NoC), although the NoC is an essential of the ULP chips, and its power consumption accounts for a significant portion of the total power. This paper focuses on ULP NoCs, and presents a new power management method that exploits delay versus temperature characteristics of ULP circuits. Recent studies on ULP circuits show that delay versus temperature characteristics are fundamentally different from normal circuits, i.e., the delay of the ULP circuits implemented in state-of-the-art bulk CMOS operating at low supply voltages or in FinFET technologies decreases with increasing temperature, a phenomenon known as the temperature effect inversion (TEI). Starting with an intuition that at a certain temperature point, power savings without Performance Penalty can be achieved by increasing the router frequency to create the opportunity to turn off some routers in ULP NoCs, or by decreasing the NoC supply voltage level, an optimization method is presented to maximize the power savings with minor Performance Penalty. To validate the proposed method, a concrete ULP NoC simulator, TEI-Noxim, has been developed. Experimental results demonstrate that TEI-aware NoC achieves an average of 36.0% power reduction over 21 applications.

  • dynamic thermal management for finfet based circuits exploiting the temperature effect inversion phenomenon
    International Symposium on Low Power Electronics and Design, 2014
    Co-Authors: Woojoo Lee, Yanzhi Wang, Tiansong Cui, Shahin Nazarian, Massoud Pedram
    Abstract:

    Due to limits on the availability of the energy source in many mobile user platforms (ranging from handheld devices to portable electronics to deeply embedded devices) and concerns about how much heat can effectively be removed from chips, minimizing the power consumption has become a primary driver for system-on-chip designers. Because of their superb characteristics, FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm CMOS technology nodes. However, based on extensive simulations, we have observed that the delay vs. temperature characteristics of FinFET-based circuits are fundamentally different from that of the conventional bulk CMOS circuits, i.e., the delay of a FinFET circuit decreases with increasing temperature even in the super-threshold supply voltage regime. Unfortunately, the leakage power dissipation of the FinFET-based circuits increases exponentially with the temperature. These two trends give rise to a tradeoff between delay and leakage power as a function of the chip temperature, and hence, lead to the definition of an optimum chip temperature operating point (i.e., one that balances concerns about the circuit speed and power efficiency.) This paper presents the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET-based circuits without any appreciable Performance Penalty. Experimental results demonstrate 40% energy saving (with no Performance Penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.

  • active bank switching for temperature control of the register file in a microprocessor
    Great Lakes Symposium on VLSI, 2007
    Co-Authors: Kimish Patel, Massoud Pedram
    Abstract:

    An effective thermal management scheme, called active bank switching, for temperature control in the register file of a microprocessor is presented. The idea is to divide the physical register file into two equal-sized banks, and to alternate between the two banks when allocating new registers to the instruction operands. Experimental results show that this periodic active bank switching scheme achieves 3.4°C of steady-state temperature reduction, with a mere 0.75% average Performance Penalty.

  • fine grained dynamic voltage and frequency scaling for precise energy and Performance tradeoff based on the ratio of off chip access to on chip computation times
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005
    Co-Authors: Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Abstract:

    This work presents an intraprocess dynamic voltage and frequency scaling (DVFS) technique targeted toward nonreal-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the Performance Penalty. The proposed DVFS technique relies on dynamically constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot and, thus, adjust its voltage and frequency in order to save energy, while meeting soft timing constraints. This is, in turn, achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a Performance degradation of 12% was achieved. For CPU-bound programs, 15% /spl sim/ 60% CPU energy saving was achieved at the cost of 5%-20% Performance Penalty.

  • a backlight power management framework for battery operated multimedia systems
    IEEE Design & Test of Computers, 2004
    Co-Authors: Hojun Shim, Naehyuck Chang, Massoud Pedram
    Abstract:

    Thin-film transistor liquid-crystal displays are systems widely used to support full-featured multimedia. For such systems, backlight is a major source of power dissipation. This article introduces a backlight power management framework and explores trade-offs in the extended dynamic-luminance-scaling design space in terms of energy reduction, Performance Penalty, and image quality.

Joaquim F. Martins-filho - One of the best experts on this subject based on the ideXlab platform.