The Experts below are selected from a list of 1137 Experts worldwide ranked by ideXlab platform
Mateo Valero - One of the best experts on this subject based on the ideXlab platform.
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An Optimized Front-End Physical Register File with Banking and Writeback Filtering
2014Co-Authors: Ruben Gonzalez, Alex Veidenbaum, Mateo ValeroAbstract:In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a central storage for all in-flight values, which offers a high performance potential. AMD, on the other hand, uses an opti-mized implementation of the Future File for its line of Opteron processors. Both approaches have limitations that may preclude there application in fu-ture processor implementations. The centralized register file scales poorly in terms of power-performance. The Future File may be limited by the requirement of distributed reservation stations and by the branch mispredic-tion recovery scheme. This paper proposes to give processor designer teams another choice by combining a traditional future file architecture with the concept of a cen-tral physical register file. This new register file is used in the ”front end” in combination with value storage in the Instruction Queue. Further, it is shown that, contrary to what happens with a centralized R10k-like architec-ture, the proposed architecture can use banking that scales well with the size of structures in the processor. Only a 0.3 % IPC degradation was observed when using this technique. The energy savings due to banking are fully utilized in our proposal. Further, the implementation is shown to integrate well with a technique to early release short lived values that we call write-back filtering. Overall, the resulting energy delay product is lower than in previous proposals
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Scalable Distributed Register File
2014Co-Authors: Ruben Gonzalez, Miquel Pericàs, Alex Veidenbaum, Mateo ValeroAbstract:Abstract — In microarchitectural design, conceptual simplicity does not always lead to reduced technological complexity. VLSI design offers several standard structures which get very inef-ficient when they are scaled up. For instance, the superscalar OOO processing model is conceptually simple – with the control-flow oriented front-end and the dataflow oriented backend – but simply scaling the structures in this architecture for wider issue soon shows several bottlenecks, particularly related to power and timing issues, In this paper we propose a superscalar architecture obtained after identifying the register file as a core bottleneck structure of a microprocessor and replacing it with a more efficient model that also scales better. Taking into account the status of the registers and the source of operands we redesigned the microarchitecture around a distributed set of Register Files and an extended Instruction Queue. We compare our architecture to widely used superscalar architectures using either a central physical/architectural register file or a Future File. We found that the traditional Future File architecture is much less scalable than our Promotional Architecture. With a 256-entry ROB, the Future File Architecture (FFA) loses 7 % speed on average I
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A Simple Low-Energy Instruction Wakeup Mechanism
2008Co-Authors: Marco A. Leyva Ramírez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Er V. Veidenbaum, Mateo ValeroAbstract:Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for Instruction wakeup, which uses a multi-block Instruction Queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks
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a new pointer based Instruction Queue design and its power performance evaluation
International Conference on Computer Design, 2005Co-Authors: Marco Leyva A Ramirez, Alexander V Veidenbaum, Adrian Cristal, Luisa F Villa, Mateo ValeroAbstract:Instruction Queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based Instruction Queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on Queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of Instruction Queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.
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a partitioned Instruction Queue to reduce Instruction wakeup energy
IEEE International Conference on High Performance Computing Data and Analytics, 2004Co-Authors: Marco Leyva A Ramirez, Alexander V Veidenbaum, Adrian Cristal, Mateo Valero, Luis VillaAbstract:Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for Instruction wakeup, which uses a partitioned Instruction Queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 µm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.
Steven K Reinhardt - One of the best experts on this subject based on the ideXlab platform.
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a scalable Instruction Queue design for exploiting parallelism
2004Co-Authors: Steven Raasch, Steven K ReinhardtAbstract:To maximize the performance of wide-issue superscalar out-of-order microprocessors, the issue stage must be able to extract as much Instruction-level parallelism (ILP) as possible from the dynamic Instruction stream. This dissertation examines several approaches to increasing available ILP while minimizing the impact on cycle time. First, I describe and evaluate a novel Instruction Queue design (the Segmented Instruction Queue) that eliminates the correspondence between IQ size and cycle time. The 512-entry Segmented IQ achieves between 58% and 98% of the performance of similarly-sized idealized Instruction Queue of conventional design though the latency of the latter is approximately 256 times larger. The Segmented IQ can be used as a component of a clustered architecture, another approach to reducing cycle-time penalties in wide-issue machines. The dependence tracking mechanism used by the Segmented IQ can be applied to the problem of Instruction placement in clustered architectures. By changing the mix of Instructions present in the IQ, simultaneous multithreading (SMT) can also be used to increase the amount of available ILP. Under SMT, partitioning schemes are needed to distribute resource among threads; however, some of these schemes, clustered architectures in particular, can significantly reduce SMT workload performance. If an SMT machine is to use a clustered microarchitecture, the choice of Instruction placement policy must be carefully evaluated to avoid performance degradation. Experiments show that naively allocating clusters to individual threads, eliminating the dynamic sharing that is the core of SMT, can reduce workload performance on a four-cluster architecture by as much as 26% versus a simple load-balancing scheme. This dissertation presents data that characterizes the performance of SMT workloads in clustered architectures using both conventional Instruction Queues and segmented Instruction Queues. Individually, these mechanisms represent viable approaches to increasing available ILP. When the Segmented IQ is used in an SMT processor design, workload performance achieves an average of 80% and 86% of the idealized performance for two- and four-thread workloads, respectively, indicating that these approaches can be combined to form an effective approach to increasing processor utilization and performance.
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a systematic methodology to compute the architectural vulnerability factors for a high performance microprocessor
International Symposium on Microarchitecture, 2003Co-Authors: Shubhendu S Mukherjee, Steven K Reinhardt, C Weaver, Joel Emer, Todd AustinAbstract:Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transients faults exist, but come at a cost. Designers clearly require accurate estimates of processor error rates to make appropriate cost/reliability tradeoffs. This paper describes a method for generating these estimates. A key aspect of this analysis is that some single-bit faults (such as those occurring in the branch predictor) do not produce an error in a program's output. We define a structure's architectural vulnerability factor (AVF) as the probability that a fault in that particular structure do not result in an error. A structure's error rate is the product of its raw error rate, as determined by process and circuit technology, and the AVF. Unfortunately, computing AVFs of complex structures, such as the Instruction Queue, can be quite involved. We identify numerous cases, such as prefetches, dynamically dead code, and wrong-path Instructions, in which a fault do not affect, correct execution. We instrument a detailed 1A64 processor simulator to map bit-level microarchitectural state to these cases, generating per-structure AVF estimates. This analysis shows AVFs of 28% and 9% for the Instruction Queue and execution units, respectively, averaged across dynamic sections of the entire CPU2000 benchmark suite.
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a scalable Instruction Queue design using dependence chains
International Symposium on Computer Architecture, 2002Co-Authors: Steven Raasch, Nathan Binkert, Steven K ReinhardtAbstract:Increasing the number of Instruction Queue (IQ) entries in a dynamically scheduled processor exposes more Instruction-level parallelism, leading to higher performance. However, increasing a conventional IQ's physical size leads to larger latencies and slower clock speeds. We introduce a new IQ design that divides a large Queue into small segments, which can be clocked at high frequencies. We use dynamic dependence-based scheduling to promote Instructions from segment to segment until they reach a small issue buffer. Our segmented IQ is designed specifically to accommodate variable-latency Instructions such as loads. Despite its roughly similar circuit complexity; simulation results indicate that our segmented Instruction Queue with 512 entries and 128 chains improves performance by up to 69% over a 32-entry conventional Instruction Queue for SpecINT 2000 benchmarks, and up to 398% for SpecFP 2000 benchmarks. The segmented IQ achieves from 55% to 98% of the performance of a monolithic 512-entry Queue while providing the potential for much higher clock speeds.
Alexander V Veidenbaum - One of the best experts on this subject based on the ideXlab platform.
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A Simple Low-Energy Instruction Wakeup Mechanism
2008Co-Authors: Marco A. Leyva Ramírez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Er V. Veidenbaum, Mateo ValeroAbstract:Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for Instruction wakeup, which uses a multi-block Instruction Queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks
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ICSAMOS - A centralized cache miss driven technique to improve processor power dissipation
2008 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation, 2008Co-Authors: Houman Homayoun, Mohammad Makhzan, Jean-luc Gaudiot, Alexander V VeidenbaumAbstract:Leakage and dynamic power are a major challenge in microprocessor design. Many circuit techniques along with micro-architectural innovations have been proposed to reduce power in individual processor units. But it is not clear that these techniques can be combined. A centralized approach which can reduce power in more than one unit at a time with minimal the hardware overhead is needed. This paper proposes such a centralized approach that attempts to simultaneously reduce power in processor units with highest dissipation: the reorder buffer, the Instruction Queue, and the integer and the floating-point register files. It is based on an observation that utilization for the aforementioned units varies significantly, during a period when an L2 cache miss or multiple L1 cache misses are pending as compared to a period when none of these are present. Therefore we propose to dynamically adjust the size and thus power dissipation of these resources during such periods. Circuit level modifications required for such resource adaptation are presented. Simulation results for SPEC2K benchmarks show a substantial reduction in both leakage and dynamic power: the total dynamic power is reduced by as much as 30, 31, 31 and 48% for the reorder buffer, the integer register file, the floating-point register file and the Instruction Queue, respectively. The reduction in leakage is up to 33% for reorder buffer and 37% for integer and floating-point register files. The total energy-delay product is reduced, on average, by 15, 26, 20 and 17% for the reorder buffer, the integer register file, the floating-point register file and the Instruction Queue respectively. This comes at the cost of a performance impact which is as low as 0.9% for integer and 2.2% for floating-point benchmarks. The required hardware modification is shown to be minimal.
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a new pointer based Instruction Queue design and its power performance evaluation
International Conference on Computer Design, 2005Co-Authors: Marco Leyva A Ramirez, Alexander V Veidenbaum, Adrian Cristal, Luisa F Villa, Mateo ValeroAbstract:Instruction Queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based Instruction Queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on Queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of Instruction Queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.
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a partitioned Instruction Queue to reduce Instruction wakeup energy
IEEE International Conference on High Performance Computing Data and Analytics, 2004Co-Authors: Marco Leyva A Ramirez, Alexander V Veidenbaum, Adrian Cristal, Mateo Valero, Luis VillaAbstract:Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for Instruction wakeup, which uses a partitioned Instruction Queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 µm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.
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Direct Instruction Wakeup for Out-of-Order Processors
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), 2004Co-Authors: M.a. Ramirez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Mateo ValeroAbstract:Instruction Queues consume a significant amount of power in high-performance processors, primarily due to Instruction wakeup logic access to the Queue structures. The wakeup logic delay is also a critical timing parameter. This paper proposes a new Queue organization using a small number of successor pointers plus a small number of dynamically allocated full successor bit vectors for cases with a larger number of successors. The details of the new organization are described and it is shown to achieve the performance of CAM-based or full dependency matrix organizations using just one pointer per Instruction plus eight full bit vectors. Only two full bit vectors are needed when two successor pointers are stored per Instruction. Finally, a design and pre-layout of all critical structures in 70 nm technology was performed for the proposed organization as well as for a CAM-based baseline. The new design is shown to use 1/2 to 1/5th of the baseline Instruction Queue power, depending on Queue size. It is also shown to use significantly less power than the full dependency matrix based design
Luis Villa - One of the best experts on this subject based on the ideXlab platform.
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A Simple Low-Energy Instruction Wakeup Mechanism
2008Co-Authors: Marco A. Leyva Ramírez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Er V. Veidenbaum, Mateo ValeroAbstract:Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for Instruction wakeup, which uses a multi-block Instruction Queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks
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a partitioned Instruction Queue to reduce Instruction wakeup energy
IEEE International Conference on High Performance Computing Data and Analytics, 2004Co-Authors: Marco Leyva A Ramirez, Alexander V Veidenbaum, Adrian Cristal, Mateo Valero, Luis VillaAbstract:Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for Instruction wakeup, which uses a partitioned Instruction Queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 µm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.
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Direct Instruction Wakeup for Out-of-Order Processors
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), 2004Co-Authors: M.a. Ramirez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Mateo ValeroAbstract:Instruction Queues consume a significant amount of power in high-performance processors, primarily due to Instruction wakeup logic access to the Queue structures. The wakeup logic delay is also a critical timing parameter. This paper proposes a new Queue organization using a small number of successor pointers plus a small number of dynamically allocated full successor bit vectors for cases with a larger number of successors. The details of the new organization are described and it is shown to achieve the performance of CAM-based or full dependency matrix organizations using just one pointer per Instruction plus eight full bit vectors. Only two full bit vectors are needed when two successor pointers are stored per Instruction. Finally, a design and pre-layout of all critical structures in 70 nm technology was performed for the proposed organization as well as for a CAM-based baseline. The new design is shown to use 1/2 to 1/5th of the baseline Instruction Queue power, depending on Queue size. It is also shown to use significantly less power than the full dependency matrix based design
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ISHPC - A Simple Low-Energy Instruction Wakeup Mechanism
Lecture Notes in Computer Science, 2003Co-Authors: Marco A. Leyva Ramírez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Mateo ValeroAbstract:Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for Instruction wakeup, which uses a multi-block Instruction Queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks.
Adrian Cristal - One of the best experts on this subject based on the ideXlab platform.
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A Simple Low-Energy Instruction Wakeup Mechanism
2008Co-Authors: Marco A. Leyva Ramírez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Er V. Veidenbaum, Mateo ValeroAbstract:Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for Instruction wakeup, which uses a multi-block Instruction Queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks
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a new pointer based Instruction Queue design and its power performance evaluation
International Conference on Computer Design, 2005Co-Authors: Marco Leyva A Ramirez, Alexander V Veidenbaum, Adrian Cristal, Luisa F Villa, Mateo ValeroAbstract:Instruction Queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based Instruction Queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on Queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of Instruction Queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.
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a partitioned Instruction Queue to reduce Instruction wakeup energy
IEEE International Conference on High Performance Computing Data and Analytics, 2004Co-Authors: Marco Leyva A Ramirez, Alexander V Veidenbaum, Adrian Cristal, Mateo Valero, Luis VillaAbstract:Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for Instruction wakeup, which uses a partitioned Instruction Queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 µm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.
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Direct Instruction Wakeup for Out-of-Order Processors
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), 2004Co-Authors: M.a. Ramirez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Mateo ValeroAbstract:Instruction Queues consume a significant amount of power in high-performance processors, primarily due to Instruction wakeup logic access to the Queue structures. The wakeup logic delay is also a critical timing parameter. This paper proposes a new Queue organization using a small number of successor pointers plus a small number of dynamically allocated full successor bit vectors for cases with a larger number of successors. The details of the new organization are described and it is shown to achieve the performance of CAM-based or full dependency matrix organizations using just one pointer per Instruction plus eight full bit vectors. Only two full bit vectors are needed when two successor pointers are stored per Instruction. Finally, a design and pre-layout of all critical structures in 70 nm technology was performed for the proposed organization as well as for a CAM-based baseline. The new design is shown to use 1/2 to 1/5th of the baseline Instruction Queue power, depending on Queue size. It is also shown to use significantly less power than the full dependency matrix based design
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ISHPC - A Simple Low-Energy Instruction Wakeup Mechanism
Lecture Notes in Computer Science, 2003Co-Authors: Marco A. Leyva Ramírez, Alexander V Veidenbaum, Adrian Cristal, Luis Villa, Mateo ValeroAbstract:Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for Instruction wakeup, which uses a multi-block Instruction Queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed Instruction for SPEC2000 benchmarks.