The Experts below are selected from a list of 8925 Experts worldwide ranked by ideXlab platform
Yale N Patt - One of the best experts on this subject based on the ideXlab platform.
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select free Instruction Scheduling logic
International Symposium on Microarchitecture, 2001Co-Authors: Mary D Brown, Jared Stark, Yale N PattAbstract:Pipelining allows processors to exploit parallelism. Unfortunately, critical loops---pieces of logic that must evaluate in a single cycle to meet IPC (Instructions Per Cycle) goals---prevent deeper pipelining. In today's processors, one of these loops is the Instruction Scheduling (wakeup and select) logic [10]. This paper describes a technique that pipelines this loop by breaking it into two smaller loops: a critical, single-cycle loop for wakeup; and a non-critical, potentially multi-cycle, loop for select. For the 12 SPECint*2000 benchmarks, a machine with two-cycle select logic (i. e., three-cycle Scheduling logic) using this technique has an average IPC 15% greater than a machine with three-cycle pipelined conventional Scheduling logic, and an IPC within 3% of a machine of the same pipeline depth and one-cycle (ideal) Scheduling logic. Since select accounts for more than half the Scheduling latency [10], this technique could significantly increase clock frequency while having minimal impact on IPC.
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on pipelining dynamic Instruction Scheduling logic
International Symposium on Microarchitecture, 2000Co-Authors: Jared W Stark, Mary D Brown, Yale N PattAbstract:A machine's performance is the product of its IPC (Instructions Per Cycle) and clock frequency. Recently, S. Palacharla et al. (1997) warned that the dynamic Instruction Scheduling logic for current machines performs an atomic operation. Either you sacrifice IPC by pipelining this logic, thereby eliminating its ability to execute dependent Instructions in consecutive cycles. Or you sacrifice clock frequency by not pipelining it, performing this atomic operation in a single long cycle. Both alternatives are unacceptable for high performance. The paper offers a third, acceptable, alternative: pipelined Scheduling with speculative wakeup. This technique pipelines the Scheduling logic without eliminating its ability to execute dependent Instructions in consecutive cycles. With this technique, you sacrifice little IPC, and no clock frequency. Our results show that on the SPECint95 benchmarks, a machine using this technique has an average IPC that is 13% greater than the IPC of a baseline machine that pipelines the Scheduling logic but sacrifices the ability to execute dependent Instructions in consecutive cycles, and within 2% of the IPC of a conventional machine that uses single cycle Scheduling logic.
Jorg Henkel - One of the best experts on this subject based on the ideXlab platform.
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Instruction Scheduling for reliability aware compilation
Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Jorg HenkelAbstract:An Instruction Scheduling technique is presented that targets at improving the reliability of a software program given a user-provided tolerable performance overhead. A look-ahead-based heuristic schedules Instructions by evaluating the reliability of dependent Instructions while reducing the impact of spatial and temporal vulnerabilities of various processor components. Our reliability-driven Instruction scheduler (implemented into the GCC compiler) provides on average a 22% reduction of program failures compared to state-of-the-art.
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raise reliability aware Instruction Scheduling for unreliable hardware
Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction Scheduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (pipeline, register file, etc.) used during the execution of different Instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical Instructions inside the pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before Instructions Scheduling). Compared to state-of-the-art reliability-aware Instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
Jonathan Rose - One of the best experts on this subject based on the ideXlab platform.
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high performance Instruction Scheduling circuits for superscalar out of order soft processors
ACM Transactions on Reconfigurable Technology and Systems, 2018Co-Authors: Henry Wong, Vaughn Betz, Jonathan RoseAbstract:Soft processors have a role to play in simplifying field-programmable gate array (FPGA) application design as they can be deployed only when needed, and it is easier to write and debug single-threaded software code than create hardware. The breadth of this second role increases when the performance of the soft processor increases, yet the sophisticated out-of-order superscalar approaches that arrived in the mid-1990s are not employed, despite their area cost now being easily tolerable. In this article, we take an important step toward out-of-order execution in soft processors by exploring Instruction Scheduling in an FPGA substrate. This differs from the hard-processor design problem because the logic substrate is restricted to LUTs, whereas hard processor Scheduling circuits employ CAM and wired-OR structures to great benefit. We discuss both circuit and microarchitectural trade-offs and compare three circuit structures for the scheduler, including a new structure called a fused-logic matrix scheduler. Using our optimized circuits, we show that four-issue distributed schedulers with up to 54 entries can be built with the same cycle time as the commercial Nios II/f soft processor (240MHz). This careful design has the potential to significantly increase both the IPC and raw compute performance of a soft processor, compared to current commercial soft processors.
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high performance Instruction Scheduling circuits for out of order soft processors
Field-Programmable Custom Computing Machines, 2016Co-Authors: Henry Wong, Vaughn Betz, Jonathan RoseAbstract:Soft processors have a role to play in easing the difficulty of designing applications into FPGAs for two reasons: first, they can be deployed only when needed, unlike permanent on-die hard processors. Second, for the portions of an application that can function sufficiently fast on a soft processor, it is far easier to write and debug single-threaded software code than to create hardware. The breadth of this second role increases when the performance of the soft processor increases, yet there has been little progress in the performance of soft processors since their commercial inception -- in particular, the sophisticated out-of-order superscalar approaches that arrived in the mid 1990s are not employed, despite the fact that their area cost is now easily tolerable. In this paper we take an important step towards out-of-order execution in soft processors by exploring Instruction Scheduling in an FPGA substrate. This differs from the hard-processor design problem because the logic substrate is restricted to LUTs, whereas hard processor Scheduling circuits employ CAM and wired-OR structures to great benefit. We discuss both circuit and microarchitectural trade-offs, and compare three circuit structures for the scheduler, including a new structure called a fused-logic matrix scheduler. With this circuit, large schedulers up to 40 entries can be built with the same cycle time as the commercial Nios II/f soft processor (240~MHz). This careful design has the potential to significantly increase both the IPC and raw compute performance of a soft processor, compared to current commercial soft processors.
E M K Lai - One of the best experts on this subject based on the ideXlab platform.
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a rough programming approach to power balanced Instruction Scheduling for vliw digital signal processors
IEEE Transactions on Signal Processing, 2008Co-Authors: Shu Xiao, E M K LaiAbstract:The focus of this paper is on VLIW Instruction Scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set theory to characterize the imprecision inherent in the Instruction-level power model that is obtained through empirical measurements. The optimal Instruction Scheduling problem based on such a power model is formulated as a chance-constrained rough program which is solved by a problem-specific genetic algorithm. Efficiency of the algorithm is greatly improved through a novel rule-based approach to rank the intermediate candidate schedules. Experimental results using the MediaBench and Trimaran benchmarks show that the near-optimal schedules obtained are significantly better than those obtained through the mixed-integer programming approach. Computational requirements are low enough for the technique to be adopted by practical compilers.
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a rough programming approach to power aware vliw Instruction Scheduling for digital signal processors
International Conference on Acoustics Speech and Signal Processing, 2005Co-Authors: Shu Xiao, E M K LaiAbstract:Current techniques for power-aware VLIW Instruction Scheduling assume that the power consumption parameters are precisely known. In reality, there is always some degree of imprecision. We propose to apply rough set theory to handle the imprecision involved. Power consumption parameters are modeled as rough variables and the power-balanced Instruction Scheduling problem is formulated as a rough program. The effectiveness and advantages of our approach are illustrated through examples.
Antonio Gonzalez - One of the best experts on this subject based on the ideXlab platform.
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graph partitioning based Instruction Scheduling for clustered processors
International Symposium on Microarchitecture, 2001Co-Authors: Alex Aleta, Jesus Sanchez, Josep M Codina, Antonio GonzalezAbstract:This paper presents a novel scheme to schedule loops for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques followed by a Scheduling phase that integrates register allocation and spill code generation. The graph partitioning scheme is shown to be very effective due to its global view of the whole code while the partition is generated. Results show a significant speedup when compared with previously proposed techniques. For some processor configuration the average speedup for the SPECfp95 is 23% with respect to the published scheme with the best performance. Besides, the proposed scheme is much faster (between 2-7 times, depending on the configuration).
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Instruction Scheduling for clustered vliw architectures
International Symposium on Systems Synthesis, 2000Co-Authors: Jesus Sanchez, Antonio GonzalezAbstract:Clustered VLIW organizations are nowadays a common trend in the design of embedded/DSP processors. In this work we propose a novel modulo Scheduling approach for such architectures. The proposed technique performs the cluster assignment and the Instruction Scheduling in a single pass, which is more effective than doing first the assignment and latter the Scheduling. We also show that loop unrolling significantly enhances the performance of the proposed scheduler, especially when the communication channel among clusters is the main performance bottleneck. By selectively unrolling some loops, we can obtain the best performance with the minimum increase in code size. Performance evaluation for the SPECfp95 shows that the clustered architecture achieves about the same IPC (Instructions Per Cycle) as a unified architecture with the same resources. Moreover, when the cycle time is taken into account, a 4-cluster configuration is 3.6 times faster than the unified architecture.