The Experts below are selected from a list of 10812 Experts worldwide ranked by ideXlab platform
Erven Rohou - One of the best experts on this subject based on the ideXlab platform.
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towards automatic binary runtime loop de parallelization using on stack replacement
Information Processing Letters, 2019Co-Authors: Marwa Yusuf, Ahmed Elmahdy, Erven RohouAbstract:Abstract Runtime compilation has opportunities to parallelize code which are generally not available using static parallelization approaches. However, the parallelized code can possibly slowdown the performance due to unforeseen parallel overheads such as synchronization and speculation support pertaining to the chosen parallelization strategy and the underlying parallel platform. Moreover, with the wide usage of heterogeneous architectures, such choice options become more pronounced. In this paper, we consider an adaptive form of the parallelization operation, for the first time. We propose a method for performing on-stack de-parallelization for a parallelized binary loop at runtime, thereby allowing for rapid loop replacement with a more optimized one. For this paper, we consider a loop parallelization strategy and propose a corresponding de-parallelization method. The method relies on stopping the execution at safe points, gathering threads' states, producing a corresponding serial code, and continuing execution serially. The decision to de-parallelize or not is taken based on the anticipated speedup. To assess the extent of our approach, we have conducted an initial study on a small set of programs with various parallelization overheads. Results show up to 4× performance improvement for a synchronization intense program on a 4-core Intel Processor.
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branch prediction and the performance of interpreters don t trust folklore
Symposium on Code Generation and Optimization, 2015Co-Authors: Erven Rohou, Bharath Narasimha Swamy, Andre SeznecAbstract:Interpreters have been used in many contexts. They provide portability and ease of development at the expense of performance. The literature of the past decade covers analysis of why interpreters are slow, and many software techniques to improve them. A large proportion of these works focuses on the dispatch loop, and in particular on the implementation of the switch statement: typically an indirect branch instruction. Folklore attributes a significant penalty to this branch, due to its high misprediction rate. We revisit this assumption, considering state-of-the-art branch predictors and the three most recent Intel Processor generations on current interpreters. Using both hardware counters on Has well, the latest Intel Processor generation, and simulation of the IT-TAGE, we show that the accuracy of indirect branch prediction is no longer critical for interpreters. We further compare the characteristics of these interpreters and analyze why the indirect branch is less important than before.
Erik Reeber - One of the best experts on this subject based on the ideXlab platform.
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replacing testing with formal verification in Intel scriptsize circledr coretm i7 Processor execution engine validation
Computer Aided Verification, 2009Co-Authors: Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodova, Christopher Taylor, Vladimir Frolov, Erik ReeberAbstract:Formal verification of arithmetic datapaths has been part of the established methodology for most Intel Processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel$^{\tiny\circledR}$ CoreTM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full datapath, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.
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replacing testing with formal verification in Intel coretm i7 Processor execution engine validation
Computer Aided Verification, 2009Co-Authors: Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodova, Christopher Taylor, Vladimir Frolov, Erik ReeberAbstract:Formal verification of arithmetic datapaths has been part of the estab- lished methodology for most Intel Processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel Core TM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full data- path, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.
Roope Kaivola - One of the best experts on this subject based on the ideXlab platform.
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replacing testing with formal verification in Intel scriptsize circledr coretm i7 Processor execution engine validation
Computer Aided Verification, 2009Co-Authors: Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodova, Christopher Taylor, Vladimir Frolov, Erik ReeberAbstract:Formal verification of arithmetic datapaths has been part of the established methodology for most Intel Processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel$^{\tiny\circledR}$ CoreTM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full datapath, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.
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replacing testing with formal verification in Intel coretm i7 Processor execution engine validation
Computer Aided Verification, 2009Co-Authors: Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodova, Christopher Taylor, Vladimir Frolov, Erik ReeberAbstract:Formal verification of arithmetic datapaths has been part of the estab- lished methodology for most Intel Processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel Core TM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full data- path, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.
Rajnish Ghughal - One of the best experts on this subject based on the ideXlab platform.
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symbolic trajectory evaluation the primary validation vehicle for next generation Intel Processor graphics fpu
Formal Methods in Computer-Aided Design, 2012Co-Authors: V Achutha M Kirankumar, Aarti Gupta, Rajnish GhughalAbstract:Formal Verification (FV) is widely acknowledged for improving validation effectiveness. Usually formal verification has been used to supplement more traditional coverage oriented testing activities. Arithmetic Data-path FV has matured over the time to completely replace traditional dynamic validation methodologies. Moreover, it gives an additional promise of 100% data-space coverage. Symbolic Trajectory Evaluation (STE) is the best proven method of FV on Intel® data-path designs. The Floating Point Units (FPUs) are generally very data-path intensive. In the next generation Intel Processor Graphics design, the FPU was completely re-architected and this necessitated a methodology which could guarantee complete verification in a tight verification schedule. STE was brought in to meet this formidable target. This paper discusses the efficient application of this methodology to achieve convincing results. More than 201 bugs were caught in a very short verification cycle using STE.
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replacing testing with formal verification in Intel scriptsize circledr coretm i7 Processor execution engine validation
Computer Aided Verification, 2009Co-Authors: Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodova, Christopher Taylor, Vladimir Frolov, Erik ReeberAbstract:Formal verification of arithmetic datapaths has been part of the established methodology for most Intel Processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel$^{\tiny\circledR}$ CoreTM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full datapath, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.
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replacing testing with formal verification in Intel coretm i7 Processor execution engine validation
Computer Aided Verification, 2009Co-Authors: Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodova, Christopher Taylor, Vladimir Frolov, Erik ReeberAbstract:Formal verification of arithmetic datapaths has been part of the estab- lished methodology for most Intel Processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel Core TM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full data- path, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.
Marwa Yusuf - One of the best experts on this subject based on the ideXlab platform.
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towards automatic binary runtime loop de parallelization using on stack replacement
Information Processing Letters, 2019Co-Authors: Marwa Yusuf, Ahmed Elmahdy, Erven RohouAbstract:Abstract Runtime compilation has opportunities to parallelize code which are generally not available using static parallelization approaches. However, the parallelized code can possibly slowdown the performance due to unforeseen parallel overheads such as synchronization and speculation support pertaining to the chosen parallelization strategy and the underlying parallel platform. Moreover, with the wide usage of heterogeneous architectures, such choice options become more pronounced. In this paper, we consider an adaptive form of the parallelization operation, for the first time. We propose a method for performing on-stack de-parallelization for a parallelized binary loop at runtime, thereby allowing for rapid loop replacement with a more optimized one. For this paper, we consider a loop parallelization strategy and propose a corresponding de-parallelization method. The method relies on stopping the execution at safe points, gathering threads' states, producing a corresponding serial code, and continuing execution serially. The decision to de-parallelize or not is taken based on the anticipated speedup. To assess the extent of our approach, we have conducted an initial study on a small set of programs with various parallelization overheads. Results show up to 4× performance improvement for a synchronization intense program on a 4-core Intel Processor.