The Experts below are selected from a list of 2268 Experts worldwide ranked by ideXlab platform

Pawel Gepner - One of the best experts on this subject based on the ideXlab platform.

  • HPCS - Evaluation of Intel Xeon E5-2600v2 based cluster for technical computing workloads
    2014 International Conference on High Performance Computing & Simulation (HPCS), 2014
    Co-Authors: Pawel Gepner, Victor Gamayunov, Wieslawa Litke, Ludovic Sauge, Cyril Mazauric
    Abstract:

    In Intel's CPU releasing model, the new Ivy Bridge is a “TICK” that follows Sandy Bridge's (“TOCK”) microarchitecture principles, however, after undergoing a die shrink it is manufactured at 22nm. It also incorporates new micro-architectural upgrades. In this paper we shall evaluate the performance of a 16 bi-socket node cluster based on this 3rd generation Intel Xeon Processor E5-2697v2 meant for server and workstation market. The new architectural improvements are assessed via High Performance Computing Challenge (HPCC) benchmarks and NAS Parallel Benchmarks (NPB) where the interconnect technology is challenged by the standard Intel® MPI Benchmark suite performance evaluator. Finally we tested performance of the new system using the subset of the benchmark from PRACE consortium. We compare achieved results against the outcomes of the tests performed on clusters based on previous generations of Intel Xeon Processors: Intel Xeon E5-2680 (“Sandy Bridge-EP”), Intel Xeon 5680 (“Westmere-EP”) and Intel Xeon 5570 (“Nehalem-EP”) respectively.

  • Performance evaluation of Intel Xeon E5-2600 family cluster using scientific and engineering benchmarks
    2012 2nd IEEE International Conference on Parallel Distributed and Grid Computing, 2012
    Co-Authors: Pawel Gepner, David L. Fraser, Victor Gamayunov
    Abstract:

    In this paper, we present an performance evaluation of a 256-core cluster based on the Intel Xeon Processor E5-2680. This is the new version of Sandy Bridge Processor for server and workstation market. It employs an integrated memory controller, dual Intel Quick Path Interconnect (QPI) port and integrated PCIe 3.0 controller. We assessed these architectural enhancements using the High Performance Computing Challenge (HPCC) benchmarks and NAS Parallel Benchmarks (NPB). For Interconnect analysis we have used the NetPIPE performance evaluator. We compare and contrast the results of a cluster based on the Intel Xeon E5-2680 with a cluster based on Intel Xeon 5680 Processor and another cluster based on Intel Xeon 5570 Processor.

  • Evaluating new architectural features of the Intel(r) Xeon(r) 7500 Processor for hpc workloads
    Computer Science, 2011
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik, Kazimierz Wackowski
    Abstract:

    In this paper we take a look at what the Intel Xeon Processor 7500 family, code namedNehalem-EX, brings to high performance computing. We compare two families of Intel Xeonbased systems (Intel Xeon 7500 and Intel Xeon 5600) and present a performance evolutionof 16 node clusters based on these CPUs. We compare CPU generations utilizing dual socketplatforms and a cluster across a number of HPC benchmarks and focused on differentperformance field and aspect. We will evaluate also technologies and features like Intels HyperThreading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and theperformance implication of these technologies for HPC.

  • PPAM (1) - Evaluating performance of new quad-core Intel®Xeon®5500 family Processors for HPC
    Parallel Processing and Applied Mathematics, 2010
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik
    Abstract:

    In this paper we take a look at what the new Quad-Core Intel Xeon Processor code name Nehalem brings to high performance computing. We compare Intel Xeon 5400 series based system with a server utilizing his successor the new Intel Xeon X5560. We compare both CPU generations utilizing dual socket platforms using a number of HPC benchmarks. The results clearly prove that the new Intel Xeon Processor 5500 family provide significant performance advantage on typical HPC workloads and demonstrate to be a right choice for many of HPC installations.

  • ISPDC - Early Performance Evaluation of New Six-Core Intel® Xeon® 5600 Family Processors for HPC
    2010 Ninth International Symposium on Parallel and Distributed Computing, 2010
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik, Kazimierz Wackowski
    Abstract:

    In this paper we take a look at what the newest member of the Intel Xeon Processor family, code named Westmere brings to high performance computing. We compare three generations of Intel Xeon based systems and present a performance evolutions based on 16 node clusters based on these CPUs respectively. We compare CPU generations utilizing dual socket platforms and a cluster across a number of HPC benchmarks and focused on different performance field and aspect. We will evaluate also technologies and features like Intel’s Hyper Threading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and the performance implication of these technologies for HPC.

Michal F. Kowalik - One of the best experts on this subject based on the ideXlab platform.

  • Evaluating new architectural features of the Intel(r) Xeon(r) 7500 Processor for hpc workloads
    Computer Science, 2011
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik, Kazimierz Wackowski
    Abstract:

    In this paper we take a look at what the Intel Xeon Processor 7500 family, code namedNehalem-EX, brings to high performance computing. We compare two families of Intel Xeonbased systems (Intel Xeon 7500 and Intel Xeon 5600) and present a performance evolutionof 16 node clusters based on these CPUs. We compare CPU generations utilizing dual socketplatforms and a cluster across a number of HPC benchmarks and focused on differentperformance field and aspect. We will evaluate also technologies and features like Intels HyperThreading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and theperformance implication of these technologies for HPC.

  • PPAM (1) - Evaluating performance of new quad-core Intel®Xeon®5500 family Processors for HPC
    Parallel Processing and Applied Mathematics, 2010
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik
    Abstract:

    In this paper we take a look at what the new Quad-Core Intel Xeon Processor code name Nehalem brings to high performance computing. We compare Intel Xeon 5400 series based system with a server utilizing his successor the new Intel Xeon X5560. We compare both CPU generations utilizing dual socket platforms using a number of HPC benchmarks. The results clearly prove that the new Intel Xeon Processor 5500 family provide significant performance advantage on typical HPC workloads and demonstrate to be a right choice for many of HPC installations.

  • ISPDC - Early Performance Evaluation of New Six-Core Intel® Xeon® 5600 Family Processors for HPC
    2010 Ninth International Symposium on Parallel and Distributed Computing, 2010
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik, Kazimierz Wackowski
    Abstract:

    In this paper we take a look at what the newest member of the Intel Xeon Processor family, code named Westmere brings to high performance computing. We compare three generations of Intel Xeon based systems and present a performance evolutions based on 16 node clusters based on these CPUs respectively. We compare CPU generations utilizing dual socket platforms and a cluster across a number of HPC benchmarks and focused on different performance field and aspect. We will evaluate also technologies and features like Intel’s Hyper Threading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and the performance implication of these technologies for HPC.

  • second generation quad core Intel Xeon Processors bring 45 nm technology and a new level of performance to hpc applications
    International Conference on Computational Science, 2008
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik
    Abstract:

    The second generation of Quad-Core Intel® Xeon® Processors was launched on November 12th 2007. In this paper we take a look at what the new 45 nm based Quad-Core Intel Xeon Processor brings to high performance computing. We compare an Intel Xeon 5300 series based system with a server utilizing his successor the Intel Xeon 5400. We measure both CPU generations operating in dual socket platforms in typical HPC benchmark scenario using some common HPC benchmarks. The results presented clearly show that the new Intel Xeon Processor 5400 family provides significant performance advantage on typical HPC workloads and would therefore be seen to be an appropriate choice for many of HPC installations.

  • ICCS (1) - Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications
    Computational Science – ICCS 2008, 2008
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik
    Abstract:

    The second generation of Quad-Core Intel® Xeon® Processors was launched on November 12th 2007. In this paper we take a look at what the new 45 nm based Quad-Core Intel Xeon Processor brings to high performance computing. We compare an Intel Xeon 5300 series based system with a server utilizing his successor the Intel Xeon 5400. We measure both CPU generations operating in dual socket platforms in typical HPC benchmark scenario using some common HPC benchmarks. The results presented clearly show that the new Intel Xeon Processor 5400 family provides significant performance advantage on typical HPC workloads and would therefore be seen to be an appropriate choice for many of HPC installations.

Olivier Deforges - One of the best experts on this subject based on the ideXlab platform.

  • 4K Real Time Software Solution of Scalable HEVC for Broadcast Video Application
    IEEE Access, 2019
    Co-Authors: Ronan Parois, Wassim Hamidouche, M. Raulet, Pierre-loup Cabarat, Naty Sidaty, Olivier Deforges
    Abstract:

    Scalable High efficiency Video Coding (SHVC) is the scalable extension of the High Efficiency Video Coding (HEVC) standard. SHVC enables spatial, quality, bit-depth, color gamut and codec scalability. The architecture of the SHVC encoder is based on multiple instances of the HEVC encoder where each instance encodes one video layer. This architecture offers several advantages of being modular and close to the native HEVC coding block scheme. However, the close-loop SHVC architecture requires the complete decoding of the reference lower-layer frames to decode a higher quality layer, which considerably increases the complexity of both encoder and decoder processes. In this paper, we propose an end-to-end 4K real time SHVC solution, including both software encoder and decoder, for video broadcast applications. The SHVC codec relies on low level optimizations for specific Intel x86 platform and parallel processing to speed-up the encoding and decoding processes. The proposed encoder enables a real time processing of 4Kp30 video in 2x spatial scalability on the 4x10-cores Intel Xeon Processor (E5-4627V3) running at 2.6 GHz. In addition, the SHVC decoder enables to decode, respectively, the lower quality layer in full HD (1920x1080p30) resolution, on ARM Neon mobile platform, and the enhancement layer in UHD (3840x2160p30), on a laptop fitted, with 4 cores Intel i7 Processor running at 2.7 GHz. Finally, experimental results have shown that the proposed solution can reach a high rate-distortion performance close to the reference SHVC reference software Model (SHM) with a speed-up of 37 and 66 in Intra and Inter coding configurations.

  • Multi-core software architecture for the scalable HEVC decoder
    2014
    Co-Authors: Wassim Hamidouche, M. Raulet, Olivier Deforges
    Abstract:

    The scalable high efficiency video coding (SHVC) standard aims to provide features of temporal, spatial and quality scalability. In this paper we investigate a pipeline and parallel software architecture for the SHVC decoder. The proposed architecture is based on the OpenHEVC software which implements the high efficiency video coding (HEVC) decoder. The architecture of the SHVC decoder enables two levels of parallelism. The first level decodes the base layer and the enhancement layers in parallel. The second level of parallelism performs the decoding of both the base layer and enhancement layers in parallel through the HEVC high level parallel processing solutions, including tile and wavefront. Up to the best of our knowledge, it is the first real time and parallel software implementation of the SHVC decoder. On an Intel Xeon Processor running at 3.2 GHz, the SHVC decoder reaches the decoding of 1600p enhancement layer at 40 fps for x1.5 spatial scalability with using six concurent threads.

  • ICASSP - Multi-core software architecture for the scalable HEVC decoder
    2014 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), 2014
    Co-Authors: Wassim Hamidouche, M. Raulet, Olivier Deforges
    Abstract:

    The scalable high efficiency video coding (SHVC) standard aims to provide features of temporal, spatial and quality scalability. In this paper we investigate a pipeline and parallel software architecture for the SHVC decoder. The proposed architecture is based on the OpenHEVC software which implements the high efficiency video coding (HEVC) decoder. The architecture of the SHVC decoder enables two levels of parallelism. The first level decodes the base layer and the enhancement layers in parallel. The second level of parallelism performs the decoding of both the base layer and enhancement layers in parallel through the HEVC high level parallel processing solutions, including tile and wavefront. Up to the best of our knowledge, it is the first real time and parallel software implementation of the SHVC decoder. On an Intel Xeon Processor running at 3.2 GHz, the SHVC decoder reaches the decoding of 1600p enhancement layer at 40 fps for x1.5 spatial scalability with using six concurent threads.

David L. Fraser - One of the best experts on this subject based on the ideXlab platform.

  • Performance evaluation of Intel Xeon E5-2600 family cluster using scientific and engineering benchmarks
    2012 2nd IEEE International Conference on Parallel Distributed and Grid Computing, 2012
    Co-Authors: Pawel Gepner, David L. Fraser, Victor Gamayunov
    Abstract:

    In this paper, we present an performance evaluation of a 256-core cluster based on the Intel Xeon Processor E5-2680. This is the new version of Sandy Bridge Processor for server and workstation market. It employs an integrated memory controller, dual Intel Quick Path Interconnect (QPI) port and integrated PCIe 3.0 controller. We assessed these architectural enhancements using the High Performance Computing Challenge (HPCC) benchmarks and NAS Parallel Benchmarks (NPB). For Interconnect analysis we have used the NetPIPE performance evaluator. We compare and contrast the results of a cluster based on the Intel Xeon E5-2680 with a cluster based on Intel Xeon 5680 Processor and another cluster based on Intel Xeon 5570 Processor.

  • Evaluating new architectural features of the Intel(r) Xeon(r) 7500 Processor for hpc workloads
    Computer Science, 2011
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik, Kazimierz Wackowski
    Abstract:

    In this paper we take a look at what the Intel Xeon Processor 7500 family, code namedNehalem-EX, brings to high performance computing. We compare two families of Intel Xeonbased systems (Intel Xeon 7500 and Intel Xeon 5600) and present a performance evolutionof 16 node clusters based on these CPUs. We compare CPU generations utilizing dual socketplatforms and a cluster across a number of HPC benchmarks and focused on differentperformance field and aspect. We will evaluate also technologies and features like Intels HyperThreading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and theperformance implication of these technologies for HPC.

  • PPAM (1) - Evaluating performance of new quad-core Intel®Xeon®5500 family Processors for HPC
    Parallel Processing and Applied Mathematics, 2010
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik
    Abstract:

    In this paper we take a look at what the new Quad-Core Intel Xeon Processor code name Nehalem brings to high performance computing. We compare Intel Xeon 5400 series based system with a server utilizing his successor the new Intel Xeon X5560. We compare both CPU generations utilizing dual socket platforms using a number of HPC benchmarks. The results clearly prove that the new Intel Xeon Processor 5500 family provide significant performance advantage on typical HPC workloads and demonstrate to be a right choice for many of HPC installations.

  • ISPDC - Early Performance Evaluation of New Six-Core Intel® Xeon® 5600 Family Processors for HPC
    2010 Ninth International Symposium on Parallel and Distributed Computing, 2010
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik, Kazimierz Wackowski
    Abstract:

    In this paper we take a look at what the newest member of the Intel Xeon Processor family, code named Westmere brings to high performance computing. We compare three generations of Intel Xeon based systems and present a performance evolutions based on 16 node clusters based on these CPUs respectively. We compare CPU generations utilizing dual socket platforms and a cluster across a number of HPC benchmarks and focused on different performance field and aspect. We will evaluate also technologies and features like Intel’s Hyper Threading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and the performance implication of these technologies for HPC.

  • second generation quad core Intel Xeon Processors bring 45 nm technology and a new level of performance to hpc applications
    International Conference on Computational Science, 2008
    Co-Authors: Pawel Gepner, David L. Fraser, Michal F. Kowalik
    Abstract:

    The second generation of Quad-Core Intel® Xeon® Processors was launched on November 12th 2007. In this paper we take a look at what the new 45 nm based Quad-Core Intel Xeon Processor brings to high performance computing. We compare an Intel Xeon 5300 series based system with a server utilizing his successor the Intel Xeon 5400. We measure both CPU generations operating in dual socket platforms in typical HPC benchmark scenario using some common HPC benchmarks. The results presented clearly show that the new Intel Xeon Processor 5400 family provides significant performance advantage on typical HPC workloads and would therefore be seen to be an appropriate choice for many of HPC installations.

Ramesh Arvapalli - One of the best experts on this subject based on the ideXlab platform.

  • an energy efficient 32 nm 20 mb shared on die l3 cache for Intel Xeon Processor e5 family
    IEEE Journal of Solid-state Circuits, 2013
    Co-Authors: Min Huang, Moty Mehalel, Ramesh Arvapalli
    Abstract:

    An energy efficient on-die 20-way set associative L3 cache of size 20 MB for the Intel® Xeon® Processor E5 family is presented. It is manufactured in the Intel's 32-nm second generation of high-K dielectric metal gate process with 9-copper metal layers. The L3 cache design uses 0.2119 um 2 cell for the high density big array and 0.2725 um 2cell for the high performance smaller arrays. The power efficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs. The effective and rich redundancy design improves both yield and low voltage operations. The L3 cache achieves more than 20-40% energy efficiency when compared to previous generations and demonstrates wide operating ranges from 1.2 GHz at below 0.7 V to greater than 4.0 GHz at above 1.0 V.

  • an energy efficient 32nm 20 mb l3 cache for Intel Xeon Processor e5 family
    Custom Integrated Circuits Conference, 2012
    Co-Authors: Min Huang, Moty Mehalel, Ramesh Arvapalli
    Abstract:

    A 20-way set associative 20MB energy efficient L3 this paper. The design uses 0.2119um2 cell and is manufactured in the 32nm second generation of high-K dielectric metal gate process with 9-copper layers. The power efficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs.