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Kees Goossens - One of the best experts on this subject based on the ideXlab platform.
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RTAS - Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers
2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016Co-Authors: Yonghui Li, Benny Akesson, Kai Lampka, Kees GoossensAbstract:In modern multi-core systems with multiple real-time (RT) applications, Memory traffic accessing the shared SDRAM is increasingly diverse, e.g., transactions have variable sizes. RT Memory Controllers with dynamic command scheduling can efficiently address the diversity by issuing appropriate commands subject to the SDRAM timing constraints. However, the scheduling dependencies between commands make it challenging to derive tight bounds for the worst-case response time (WCRT) and the worst-case bandwidth (WCBW) of a Memory Controller. Existing modeling and analysis techniques either do not provide tight WCRT and WCBW bounds for diverse Memory traffic with variable transaction sizes or are difficult to adapt to different RT Memory Controllers. This paper models a Memory Controller using Timed Automata (TA), where model checking is applied for analysis. Our TA model is modular and accurately captures the behavior of a RT Memory Controller with dynamic command scheduling. We obtain WCRT and WCBW bounds, which are validated by simulating the worst- case transaction traces obtained by model checking with a cycle-accurate model of the Memory Controller. Our method outperforms three state-of-the-art analysis techniques. We reduce WCRT bound by up to 20%, while the average improvement is 7.7%, and increase the WCBW bound by up to 25% with an average improvement of 13.6%. In addition, our modeling is generic enough to extend to Memory Controllers with different mechanisms.
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Reconfigurable Real-Time Memory Controller Architecture
Embedded Systems, 2016Co-Authors: Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees GoossensAbstract:Background information on SDRAM technology is provided in Sect. 2.1. The properties of pattern-based Memory Controllers are introduced in Sect. 2.2. The story continues with a detailed description of our novel reconfigurable Memory Controller architecture in Sect. 2.3. In Sect. 2.4, we derive a worst-case performance model for this Memory Controller architecture, based on a Latency-rate server abstraction. We then continue with a discussion on the implementation of a hardware instance on FPGA in Sect. 2.5, followed by a cost evaluation in Sect. 2.6.
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Architecture and analysis of a dynamically-scheduled real-time Memory Controller
Real-time Systems, 2015Co-Authors: Yonghui Li, Benny Akesson, Kees GoossensAbstract:Memory Controller design is challenging as mixed time-criticality embedded systems feature an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case response time (WCRT) of Memory transactions must be provided to RT applications, while the lowest possible average response time must be given to the remaining applications. Existing real-time Memory Controllers cannot efficiently achieve this goal as they either bound the WCRT by sacrificing the average response time, or cannot efficiently support variable transaction sizes. In this article, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this article are: (1) a Memory Controller architecture consisting of a front-end and a back-end, where the former uses a TDM arbiter with a new work-conserving policy and the latter has a dynamic command scheduling algorithm that is independent of the front-end, (2) a formalization of the timings of the Memory transactions for the proposed algorithm and architecture, and (3) an analysis of WCRT for transactions to capture the behavior of both the front-end and the back-end. This WCRT analysis supports variable transaction sizes and different degrees of bank parallelism. The critical part of the WCRT is the worst-case execution time (WCET) of a transaction, which is the time spent on command scheduling in the back-end. The WCET is bounded by two techniques applied to both fixed and variable transaction sizes, respectively. We experimentally evaluate the proposed Memory Controller and compare to an existing semi-static approach. The results demonstrate that dynamic command scheduling significantly outperforms the semi-static approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions. The former reduces the average response time for NRT applications, and the latter pertains the WCRT for RT applications.
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ECRTS - Dynamic Command Scheduling for Real-Time Memory Controllers
2014 26th Euromicro Conference on Real-Time Systems, 2014Co-Authors: Yonghui Li, Benny Akesson, Kees GoossensAbstract:Memory Controller design is challenging as real-time embedded systems feature an increasing diversity of real-time and non-real-time applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case execution time (WCET) of Memory transactions must be provided to real-time applications, while the lowest possible average execution time must be given to the rest. Existing real-time Memory Controllers cannot efficiently achieve this goal as they either bound the WCET by sacrificing the average execution time, or are not scalable to directly support variable transaction sizes, or both. In this paper, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this paper are: 1) a back-end architecture for a real-time Memory Controller with a dynamic command scheduling algorithm, 2) a formalization of the timings of the Memory transactions for the proposed architecture and algorithm, and 3) two techniques to bound the WCET of transactions with both fixed and variable sizes, respectively. We experimentally evaluate the proposed Memory Controller and compare both the worst-case and average-case execution times of transactions to a state-of-the-art semi-static approach. The results demonstrate that dynamic command scheduling outperforms the semi-static approach by 33.4% in the average case and performs at least equally well in the worst case. We also show the WCET is tight for transactions with fixed and variable sizes, respectively.
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architecture and optimal configuration of a real time multi channel Memory Controller
Design Automation and Test in Europe, 2013Co-Authors: Manil Dev Gomony, Benny Akesson, Kees GoossensAbstract:Optimal utilization of a multi-channel Memory, such as Wide IO DRAM, as shared Memory in multi-processor platforms depends on the mapping of Memory clients to the Memory channels, the granularity at which the Memory requests are interleaved in each channel, and the bandwidth and Memory capacity allocated to each Memory client in each channel. Firm real-time applications in such platforms impose strict requirements on shared Memory bandwidth and latency, which must be guaranteed at design-time to reduce verification effort. However, there is currently no real-time Memory Controller for multichannel memories, and there is no methodology to optimally configure multi-channel memories in real-time systems. This paper has four key contributions: (1) A real-time multi-channel Memory Controller architecture with a new programmable Multi-Channel Interleaver unit. (2) A novel method for logical-to-physical address translation that enables interleaving Memory requests across multiple Memory channels at different granularities. (3) An optimal algorithm based on an Integer Linear Program (ILP) formulation to map Memory clients to Memory channels considering their communication dependencies, and to configure the Memory Controller for minimum bandwidth utilization. (4) We experimentally evaluate the run-time of the algorithm and show that an optimal solution can be found within 15 minutes for realistically sized problems. We also demonstrate configuring a multi-channel Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the effectiveness of our approach.
Benny Akesson - One of the best experts on this subject based on the ideXlab platform.
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RTAS - Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers
2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016Co-Authors: Yonghui Li, Benny Akesson, Kai Lampka, Kees GoossensAbstract:In modern multi-core systems with multiple real-time (RT) applications, Memory traffic accessing the shared SDRAM is increasingly diverse, e.g., transactions have variable sizes. RT Memory Controllers with dynamic command scheduling can efficiently address the diversity by issuing appropriate commands subject to the SDRAM timing constraints. However, the scheduling dependencies between commands make it challenging to derive tight bounds for the worst-case response time (WCRT) and the worst-case bandwidth (WCBW) of a Memory Controller. Existing modeling and analysis techniques either do not provide tight WCRT and WCBW bounds for diverse Memory traffic with variable transaction sizes or are difficult to adapt to different RT Memory Controllers. This paper models a Memory Controller using Timed Automata (TA), where model checking is applied for analysis. Our TA model is modular and accurately captures the behavior of a RT Memory Controller with dynamic command scheduling. We obtain WCRT and WCBW bounds, which are validated by simulating the worst- case transaction traces obtained by model checking with a cycle-accurate model of the Memory Controller. Our method outperforms three state-of-the-art analysis techniques. We reduce WCRT bound by up to 20%, while the average improvement is 7.7%, and increase the WCBW bound by up to 25% with an average improvement of 13.6%. In addition, our modeling is generic enough to extend to Memory Controllers with different mechanisms.
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Reconfigurable Real-Time Memory Controller Architecture
Embedded Systems, 2016Co-Authors: Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees GoossensAbstract:Background information on SDRAM technology is provided in Sect. 2.1. The properties of pattern-based Memory Controllers are introduced in Sect. 2.2. The story continues with a detailed description of our novel reconfigurable Memory Controller architecture in Sect. 2.3. In Sect. 2.4, we derive a worst-case performance model for this Memory Controller architecture, based on a Latency-rate server abstraction. We then continue with a discussion on the implementation of a hardware instance on FPGA in Sect. 2.5, followed by a cost evaluation in Sect. 2.6.
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Architecture and analysis of a dynamically-scheduled real-time Memory Controller
Real-time Systems, 2015Co-Authors: Yonghui Li, Benny Akesson, Kees GoossensAbstract:Memory Controller design is challenging as mixed time-criticality embedded systems feature an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case response time (WCRT) of Memory transactions must be provided to RT applications, while the lowest possible average response time must be given to the remaining applications. Existing real-time Memory Controllers cannot efficiently achieve this goal as they either bound the WCRT by sacrificing the average response time, or cannot efficiently support variable transaction sizes. In this article, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this article are: (1) a Memory Controller architecture consisting of a front-end and a back-end, where the former uses a TDM arbiter with a new work-conserving policy and the latter has a dynamic command scheduling algorithm that is independent of the front-end, (2) a formalization of the timings of the Memory transactions for the proposed algorithm and architecture, and (3) an analysis of WCRT for transactions to capture the behavior of both the front-end and the back-end. This WCRT analysis supports variable transaction sizes and different degrees of bank parallelism. The critical part of the WCRT is the worst-case execution time (WCET) of a transaction, which is the time spent on command scheduling in the back-end. The WCET is bounded by two techniques applied to both fixed and variable transaction sizes, respectively. We experimentally evaluate the proposed Memory Controller and compare to an existing semi-static approach. The results demonstrate that dynamic command scheduling significantly outperforms the semi-static approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions. The former reduces the average response time for NRT applications, and the latter pertains the WCRT for RT applications.
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ECRTS - Dynamic Command Scheduling for Real-Time Memory Controllers
2014 26th Euromicro Conference on Real-Time Systems, 2014Co-Authors: Yonghui Li, Benny Akesson, Kees GoossensAbstract:Memory Controller design is challenging as real-time embedded systems feature an increasing diversity of real-time and non-real-time applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case execution time (WCET) of Memory transactions must be provided to real-time applications, while the lowest possible average execution time must be given to the rest. Existing real-time Memory Controllers cannot efficiently achieve this goal as they either bound the WCET by sacrificing the average execution time, or are not scalable to directly support variable transaction sizes, or both. In this paper, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this paper are: 1) a back-end architecture for a real-time Memory Controller with a dynamic command scheduling algorithm, 2) a formalization of the timings of the Memory transactions for the proposed architecture and algorithm, and 3) two techniques to bound the WCET of transactions with both fixed and variable sizes, respectively. We experimentally evaluate the proposed Memory Controller and compare both the worst-case and average-case execution times of transactions to a state-of-the-art semi-static approach. The results demonstrate that dynamic command scheduling outperforms the semi-static approach by 33.4% in the average case and performs at least equally well in the worst case. We also show the WCET is tight for transactions with fixed and variable sizes, respectively.
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architecture and optimal configuration of a real time multi channel Memory Controller
Design Automation and Test in Europe, 2013Co-Authors: Manil Dev Gomony, Benny Akesson, Kees GoossensAbstract:Optimal utilization of a multi-channel Memory, such as Wide IO DRAM, as shared Memory in multi-processor platforms depends on the mapping of Memory clients to the Memory channels, the granularity at which the Memory requests are interleaved in each channel, and the bandwidth and Memory capacity allocated to each Memory client in each channel. Firm real-time applications in such platforms impose strict requirements on shared Memory bandwidth and latency, which must be guaranteed at design-time to reduce verification effort. However, there is currently no real-time Memory Controller for multichannel memories, and there is no methodology to optimally configure multi-channel memories in real-time systems. This paper has four key contributions: (1) A real-time multi-channel Memory Controller architecture with a new programmable Multi-Channel Interleaver unit. (2) A novel method for logical-to-physical address translation that enables interleaving Memory requests across multiple Memory channels at different granularities. (3) An optimal algorithm based on an Integer Linear Program (ILP) formulation to map Memory clients to Memory channels considering their communication dependencies, and to configure the Memory Controller for minimum bandwidth utilization. (4) We experimentally evaluate the run-time of the algorithm and show that an optimal solution can be found within 15 minutes for realistically sized problems. We also demonstrate configuring a multi-channel Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the effectiveness of our approach.
Engin Ipek - One of the best experts on this subject based on the ideXlab platform.
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A programmable Memory Controller for the DDRx interfacing standards
ACM Transactions on Computer Systems, 2013Co-Authors: Nazm Bojnordi, Engin IpekAbstract:Modern Memory Controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these Controllers is to make them programmable—a proven technique that has seen wide use in other control tasks, ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx Controllers to fixed-function hardware. This article presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable Memory Controller that can meet the performance requirements of a high-speed DDRx interface. The proposed Controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the average performance of PARDIS comes within 8p of fixed-function hardware for each of these techniques; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6 to 17p and reduces DRAM energy by 9 to 22p over four existing Memory Controllers.
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ISCA - PARDIS: a programmable Memory Controller for the DDRx interfacing standards
ACM SIGARCH Computer Architecture News, 2012Co-Authors: Nazm Bojnordi, Engin IpekAbstract:Modern Memory Controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these Controllers is to make them programmable---a proven technique that has seen wide use in other control tasks ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx Controllers to fixed-function hardware. This paper presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable Memory Controller that can meet the performance requirements of a high-speed DDRx interface. The proposed Controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the average performance of PARDIS comes within 8% of fixed-function hardware for each of these techniques; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6--17% and reduces DRAM energy by 9--22% over four existing Memory Controllers.
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pardis a programmable Memory Controller for the ddrx interfacing standards
International Symposium on Computer Architecture, 2012Co-Authors: Mahdi Nazm Bojnordi, Engin IpekAbstract:Modern Memory Controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these Controllers is to make them programmable---a proven technique that has seen wide use in other control tasks ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx Controllers to fixed-function hardware. This paper presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable Memory Controller that can meet the performance requirements of a high-speed DDRx interface. The proposed Controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the average performance of PARDIS comes within 8% of fixed-function hardware for each of these techniques; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6--17% and reduces DRAM energy by 9--22% over four existing Memory Controllers.
Mahdi Nazm Bojnordi - One of the best experts on this subject based on the ideXlab platform.
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pardis a programmable Memory Controller for the ddrx interfacing standards
International Symposium on Computer Architecture, 2012Co-Authors: Mahdi Nazm Bojnordi, Engin IpekAbstract:Modern Memory Controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these Controllers is to make them programmable---a proven technique that has seen wide use in other control tasks ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx Controllers to fixed-function hardware. This paper presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable Memory Controller that can meet the performance requirements of a high-speed DDRx interface. The proposed Controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the average performance of PARDIS comes within 8% of fixed-function hardware for each of these techniques; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6--17% and reduces DRAM energy by 9--22% over four existing Memory Controllers.
Markus Ringhofer - One of the best experts on this subject based on the ideXlab platform.
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CODES+ISSS - Predator: a predictable SDRAM Memory Controller
Proceedings of the 5th IEEE ACM international conference on Hardware software codesign and system synthesis - CODES+ISSS '07, 2007Co-Authors: Benny Akesson, Kees Goossens, Markus RinghoferAbstract:Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared between a multitude of IPs to satisfy these requirements at a low cost per bit. However, SDRAMs have highly variable access times that depend on previous requests. This makes it difficult to accurately and analytically determine latencies and the useful bandwidth at design time, and hence to guarantee that hard real-time requirements are met. The main contribution of this paper is a Memory Controller design that provides a guaranteed minimum bandwidth and a maximum latency bound to the IPs. This is accomplished using a novel two-step approach to predictable SDRAM sharing. First, we define Memory access groups, corresponding to precomputed sequences of SDRAM commands, with known efficiency and latency. Second, a predictable arbiter is used to schedule these groups dynamically at run-time, such that an allocated bandwidth and a maximum latency bound is guaranteed to the IPs. The approach is general and covers all generations of SDRAM. We present a modular implementation of our Memory Controller that is efficientlyintegrated into the network interface of a network-on-chip. The area of the implementation is cheap, and scales linearly with the number of IPs. An instance with six ports runs at 200 MHz and requires 0.042mm2 in 0.13μm CMOS technology.
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predator a predictable sdram Memory Controller
International Conference on Hardware Software Codesign and System Synthesis, 2007Co-Authors: Benny Akesson, Kees Goossens, Markus RinghoferAbstract:Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared between a multitude of IPs to satisfy these requirements at a low cost per bit. However, SDRAMs have highly variable access times that depend on previous requests. This makes it difficult to accurately and analytically determine latencies and the useful bandwidth at design time, and hence to guarantee that hard real-time requirements are met. The main contribution of this paper is a Memory Controller design that provides a guaranteed minimum bandwidth and a maximum latency bound to the IPs. This is accomplished using a novel two-step approach to predictable SDRAM sharing. First, we define Memory access groups, corresponding to precomputed sequences of SDRAM commands, with known efficiency and latency. Second, a predictable arbiter is used to schedule these groups dynamically at run-time, such that an allocated bandwidth and a maximum latency bound is guaranteed to the IPs. The approach is general and covers all generations of SDRAM. We present a modular implementation of our Memory Controller that is efficientlyintegrated into the network interface of a network-on-chip. The area of the implementation is cheap, and scales linearly with the number of IPs. An instance with six ports runs at 200 MHz and requires 0.042mm2 in 0.13μm CMOS technology.
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Design and Implementation of a Memory Controller for Real-Time Applications
2006Co-Authors: Markus RinghoferAbstract:A Memory Controller is proposed where the behavior is predictable and which can be used for real-time systems. The Memory Controller is designed to be used in any system where a predictable Memory Controller is required, but integrates very well with AEthereal. It offers predictability per flow, which guarantees minimum bandwidth and maximum latency, without the necessity of simulation. Furthermore, the Memory Controller translates the peak Memory bandwidth (gross bandwidth) to a net bandwidth, which is the effective available bandwidth for the IP blocks. The proposed solution has a worst-case gross-tonet bandwidth translation efficiency of 80%. The maximum latency for the highest priority requestor is 375ns. The Memory Controller is synthesized for CMOS12 and results in a small scalable Memory Controller with 0.04mm2 for 6 requestors.