The Experts below are selected from a list of 315 Experts worldwide ranked by ideXlab platform
Wolfgang Rosenstiel - One of the best experts on this subject based on the ideXlab platform.
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simultime context sensitive timing simulation on Intermediate Code representation for rapid platform explorations
Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive simulations provide attractive benefits for timing analysis. Nevertheless, these simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive timing simulation based on the software Intermediate representation. The assured simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average simulation throughput by 90% when at least four configurations are analyzed in parallel.
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ASP-DAC - SIMULTime: Context-sensitive timing simulation on Intermediate Code representation for rapid platform explorations
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive simulations provide attractive benefits for timing analysis. Nevertheless, these simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive timing simulation based on the software Intermediate representation. The assured simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average simulation throughput by 90% when at least four configurations are analyzed in parallel.
Alessandro Cornaglia - One of the best experts on this subject based on the ideXlab platform.
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simultime context sensitive timing simulation on Intermediate Code representation for rapid platform explorations
Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive simulations provide attractive benefits for timing analysis. Nevertheless, these simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive timing simulation based on the software Intermediate representation. The assured simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average simulation throughput by 90% when at least four configurations are analyzed in parallel.
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ASP-DAC - SIMULTime: Context-sensitive timing simulation on Intermediate Code representation for rapid platform explorations
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive simulations provide attractive benefits for timing analysis. Nevertheless, these simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive timing simulation based on the software Intermediate representation. The assured simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average simulation throughput by 90% when at least four configurations are analyzed in parallel.
Norihisa Doi - One of the best experts on this subject based on the ideXlab platform.
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regression test selection based on Intermediate Code for virtual machines
International Conference on Software Maintenance, 2003Co-Authors: Toshihiko Koju, Shingo Takada, Norihisa DoiAbstract:Regression testing is testing applied to software that has been modified. It basically entails re-testing the software with previous test cases to confirm that the modifications made to the software do not have an adverse effect. But re-executing all test cases is normally cost prohibitive, and thus much research has been done on selecting test cases from a test suite without compromising the reliability of the software. These regression test selection techniques find test cases that will not detect any bugs in the modified software, and delete those from the next regression test suite. However, these techniques are based on analysis of source Code. Recent programming environments have seen a proliferation of virtual machines. For example, programs written in Java and with the Microsoft .Net Framework are compiled into a platform-independent Intermediate Code which is executed. Such Code could also be used for regression test selection. This especially holds for the Microsoft .Net Framework which handles various programming languages, such as Visual Basic and C++. Thus, this paper presents a safe regression test selection technique for virtual machine based programs. We especially target the Microsoft .Net Framework. Evaluation on 10 different examples resulted in an average of a 40.4% decrease in the cost of regression testing.
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ICSM - Regression test selection based on Intermediate Code for virtual machines
International Conference on Software Maintenance 2003. ICSM 2003. Proceedings., 1Co-Authors: Toshihiko Koju, Shingo Takada, Norihisa DoiAbstract:Regression testing is testing applied to software that has been modified. It basically entails re-testing the software with previous test cases to confirm that the modifications made to the software do not have an adverse effect. But re-executing all test cases is normally cost prohibitive, and thus much research has been done on selecting test cases from a test suite without compromising the reliability of the software. These regression test selection techniques find test cases that will not detect any bugs in the modified software, and delete those from the next regression test suite. However, these techniques are based on analysis of source Code. Recent programming environments have seen a proliferation of virtual machines. For example, programs written in Java and with the Microsoft .Net Framework are compiled into a platform-independent Intermediate Code which is executed. Such Code could also be used for regression test selection. This especially holds for the Microsoft .Net Framework which handles various programming languages, such as Visual Basic and C++. Thus, this paper presents a safe regression test selection technique for virtual machine based programs. We especially target the Microsoft .Net Framework. Evaluation on 10 different examples resulted in an average of a 40.4% decrease in the cost of regression testing.
João Rafael De Oliveira Dias - One of the best experts on this subject based on the ideXlab platform.
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resourceable retargetable modular instruction selection using a machine independent type based tiling of low level Intermediate Code
Symposium on Principles of Programming Languages, 2011Co-Authors: Norman F. Ramsey, João Rafael De Oliveira DiasAbstract:We present a novel variation on the standard technique of selecting instructions by tiling an Intermediate-Code tree. Typical compilers use a different set of tiles for every target machine. By analyzing a formal model of machine-level computation, we have developed a single set of tiles that is machine-independent while retaining the expressive power of machine Code. Using this tileset, we reduce the number of tilers required from one per machine to one per architectural family (e.g., register architecture or stack architecture). Because the tiler is the part of the instruction selector that is most difficult to reason about, our technique makes it possible to retarget an instruction selector with significantly less effort than standard techniques. Retargeting effort is further reduced by applying an earlier result which generates the machine-dependent implementation of our tileset automatically from a declarative description of instructions' semantics. Our design has the additional benefit of enabling modular reasoning about three aspects of Code generation that are not typically separated: the semantics of the compiler's Intermediate representation, the semantics of the target instruction set, and the techniques needed to generate good target Code.
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POPL - Resourceable, retargetable, modular instruction selection using a machine-independent, type-based tiling of low-level Intermediate Code
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '11, 2011Co-Authors: Norman F. Ramsey, João Rafael De Oliveira DiasAbstract:We present a novel variation on the standard technique of selecting instructions by tiling an Intermediate-Code tree. Typical compilers use a different set of tiles for every target machine. By analyzing a formal model of machine-level computation, we have developed a single set of tiles that is machine-independent while retaining the expressive power of machine Code. Using this tileset, we reduce the number of tilers required from one per machine to one per architectural family (e.g., register architecture or stack architecture). Because the tiler is the part of the instruction selector that is most difficult to reason about, our technique makes it possible to retarget an instruction selector with significantly less effort than standard techniques. Retargeting effort is further reduced by applying an earlier result which generates the machine-dependent implementation of our tileset automatically from a declarative description of instructions' semantics. Our design has the additional benefit of enabling modular reasoning about three aspects of Code generation that are not typically separated: the semantics of the compiler's Intermediate representation, the semantics of the target instruction set, and the techniques needed to generate good target Code.
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POPL - Automatically generating instruction selectors using declarative machine descriptions
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '10, 2010Co-Authors: João Rafael De Oliveira Dias, Norman F. RamseyAbstract:Despite years of work on retargetable compilers, creating a good, reliable back end for an optimizing compiler still entails a lot of hard work. Moreover, a critical component of the back end---the instruction selector---must be written by a person who is expert in both the compiler's Intermediate Code and the target machine's instruction set. By generating the instruction selector from declarative machine descriptions we have (a) made it unnecessary for one person to be both a compiler expert and a machine expert, and (b) made creating an optimizing back end easier than ever before. Our achievement rests on two new results. First, finding a mapping from Intermediate Code to machine Code is an undecidable problem. Second, using heuristic search, we can find mappings for machines of practical interest in at most a few minutes of CPU time. Our most significant new idea is that heuristic search should be controlled by algebraic laws. Laws are used not only to show when a sequence of instructions implements part of an Intermediate Code, but also to limit the search: we drop a sequence of instructions not when it gets too long or when it computes too complicated a result, but when too much reasoning will be required to show that the result computed might be useful.
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CC - Converting Intermediate Code to assembly Code using declarative machine descriptions
Lecture Notes in Computer Science, 2006Co-Authors: João Rafael De Oliveira Dias, Norman F. RamseyAbstract:Writing an optimizing back end is expensive, in part because it requires mastery of both a target machine and a compiler's internals. We separate these concerns by isolating target-machine knowledge in declarative machine descriptions. We then analyze these descriptions to automatically generate machine-specific components of the back end. In this work, we generate a recognizer; this component, which identifies register transfers that correspond to target-machine instructions, plays a key role in instruction selection in such compilers as vpo, gcc and Quick C–. We present analyses and transformations that address the major challenge in generating a recognizer: accounting for compile-time abstractions not present in a machine description, including variables, pseudo-registers, stack slots, and labels.
Oliver Bringmann - One of the best experts on this subject based on the ideXlab platform.
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simultime context sensitive timing simulation on Intermediate Code representation for rapid platform explorations
Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive simulations provide attractive benefits for timing analysis. Nevertheless, these simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive timing simulation based on the software Intermediate representation. The assured simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average simulation throughput by 90% when at least four configurations are analyzed in parallel.
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ASP-DAC - SIMULTime: Context-sensitive timing simulation on Intermediate Code representation for rapid platform explorations
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive simulations provide attractive benefits for timing analysis. Nevertheless, these simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive timing simulation based on the software Intermediate representation. The assured simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average simulation throughput by 90% when at least four configurations are analyzed in parallel.
