The Experts below are selected from a list of 7329 Experts worldwide ranked by ideXlab platform
M Aoki - One of the best experts on this subject based on the ideXlab platform.
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sub 1 v swing Internal Bus architecture for future low power ulsis
IEEE Journal of Solid-state Circuits, 1993Co-Authors: Y Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, M AokiAbstract:A Bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of Bus driver circuits and Bus receiver circuits to reduce the Bus signal swing while maintaining a low standby current. The Bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an Internal supply voltage corresponding to the reduced signal swing. The Bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new Bus driver and receiver enables the Bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >
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sub 1 v swing Internal Bus architecture for future low power ulsis
IEEE Journal of Solid-state Circuits, 1993Co-Authors: Y Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, M AokiAbstract:A Bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of Bus driver circuits and Bus receiver circuits to reduce the Bus signal swing while maintaining a low standby current. The Bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an Internal supply voltage corresponding to the reduced signal swing. The Bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new Bus driver and receiver enables the Bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >
Yuji Hatano - One of the best experts on this subject based on the ideXlab platform.
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data dependent logic swing Internal Bus architecture for ultralow power lsi s
IEEE Journal of Solid-state Circuits, 1995Co-Authors: Mitsuru Hiraki, Hirotsugu Kojima, H Misawa, T Akazawa, Yuji HatanoAbstract:A reduced-swing Internal Bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing Bus (DDL Bus) uses charge sharing between Bus wires and an additional Bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed Bus is reduced to 1/16 that of a conventional Bus when used for a 16-b-wide Bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing Bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-/spl mu/m CMOS process verify the low-power operation of the proposed Bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V. >
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data dependent logic swing Internal Bus architecture for ultra low power lsis
Symposium on VLSI Circuits, 1994Co-Authors: Mitsuru Hiraki, Hirotsugu Kojima, H Misawa, T Akazawa, Yuji HatanoAbstract:A reduced-swing Internal Bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing Bus (DDL Bus) uses charge sharing between Bus wires and an additional Bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed Bus is reduced to 1/16 that of a conventional Bus when used for a 16-b-wide Bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing Bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed Bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V
Y Nakagome - One of the best experts on this subject based on the ideXlab platform.
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sub 1 v swing Internal Bus architecture for future low power ulsis
IEEE Journal of Solid-state Circuits, 1993Co-Authors: Y Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, M AokiAbstract:A Bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of Bus driver circuits and Bus receiver circuits to reduce the Bus signal swing while maintaining a low standby current. The Bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an Internal supply voltage corresponding to the reduced signal swing. The Bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new Bus driver and receiver enables the Bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >
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sub 1 v swing Internal Bus architecture for future low power ulsis
IEEE Journal of Solid-state Circuits, 1993Co-Authors: Y Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, M AokiAbstract:A Bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of Bus driver circuits and Bus receiver circuits to reduce the Bus signal swing while maintaining a low standby current. The Bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an Internal supply voltage corresponding to the reduced signal swing. The Bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new Bus driver and receiver enables the Bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >
Mitsuru Hiraki - One of the best experts on this subject based on the ideXlab platform.
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data dependent logic swing Internal Bus architecture for ultralow power lsi s
IEEE Journal of Solid-state Circuits, 1995Co-Authors: Mitsuru Hiraki, Hirotsugu Kojima, H Misawa, T Akazawa, Yuji HatanoAbstract:A reduced-swing Internal Bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing Bus (DDL Bus) uses charge sharing between Bus wires and an additional Bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed Bus is reduced to 1/16 that of a conventional Bus when used for a 16-b-wide Bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing Bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-/spl mu/m CMOS process verify the low-power operation of the proposed Bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V. >
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data dependent logic swing Internal Bus architecture for ultra low power lsis
Symposium on VLSI Circuits, 1994Co-Authors: Mitsuru Hiraki, Hirotsugu Kojima, H Misawa, T Akazawa, Yuji HatanoAbstract:A reduced-swing Internal Bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing Bus (DDL Bus) uses charge sharing between Bus wires and an additional Bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed Bus is reduced to 1/16 that of a conventional Bus when used for a 16-b-wide Bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing Bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed Bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V
Kiyoo Itoh - One of the best experts on this subject based on the ideXlab platform.
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sub 1 v swing Internal Bus architecture for future low power ulsis
IEEE Journal of Solid-state Circuits, 1993Co-Authors: Y Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, M AokiAbstract:A Bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of Bus driver circuits and Bus receiver circuits to reduce the Bus signal swing while maintaining a low standby current. The Bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an Internal supply voltage corresponding to the reduced signal swing. The Bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new Bus driver and receiver enables the Bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >
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sub 1 v swing Internal Bus architecture for future low power ulsis
IEEE Journal of Solid-state Circuits, 1993Co-Authors: Y Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, M AokiAbstract:A Bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of Bus driver circuits and Bus receiver circuits to reduce the Bus signal swing while maintaining a low standby current. The Bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an Internal supply voltage corresponding to the reduced signal swing. The Bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new Bus driver and receiver enables the Bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >