Interrupt Mechanism

14,000,000 Leading Edge Experts on the ideXlab platform

Scan Science and Technology

Contact Leading Edge Experts & Companies

Scan Science and Technology

Contact Leading Edge Experts & Companies

The Experts below are selected from a list of 2793 Experts worldwide ranked by ideXlab platform

Obninsk Russia - One of the best experts on this subject based on the ideXlab platform.

  • Alexey Burtsev. Interrupt Mechanism for threaded code interpreter. 1 Interrupt Mechanism for threaded code interpreter
    2012
    Co-Authors: Alexey A. Burtsev, Obninsk Russia
    Abstract:

    Various methods to support Interrupt Mechanism in programming systems, based on threaded code techniques, are analysed. Threaded code interpreters, which support Interrupt handling at the level of machine code, have serious demerits. Another method of Interruption for interpreter of threaded code are suggested. It makes possible to Interrupt program only at the level of threaded code. It means, that body of Interrupt handler will be executed not at the same moment, when the Interruption is raised, but just after that moment, when the interpreter completes execution of its current command (primitive procedure, which body are defined in machine code). Realization of Interrupt Mechanism according to this suggested method for DSSP (Forth-like system, developed in Moscow University) are described. Advantages of new Interrupt technique for threaded code interpreter, especially concerning parallel programming and exception handling, are explained

Alexey A. Burtsev - One of the best experts on this subject based on the ideXlab platform.

  • Alexey Burtsev. Interrupt Mechanism for threaded code interpreter. 1 Interrupt Mechanism for threaded code interpreter
    2012
    Co-Authors: Alexey A. Burtsev, Obninsk Russia
    Abstract:

    Various methods to support Interrupt Mechanism in programming systems, based on threaded code techniques, are analysed. Threaded code interpreters, which support Interrupt handling at the level of machine code, have serious demerits. Another method of Interruption for interpreter of threaded code are suggested. It makes possible to Interrupt program only at the level of threaded code. It means, that body of Interrupt handler will be executed not at the same moment, when the Interruption is raised, but just after that moment, when the interpreter completes execution of its current command (primitive procedure, which body are defined in machine code). Realization of Interrupt Mechanism according to this suggested method for DSSP (Forth-like system, developed in Moscow University) are described. Advantages of new Interrupt technique for threaded code interpreter, especially concerning parallel programming and exception handling, are explained

Mohammadi Raeissi Masoume - One of the best experts on this subject based on the ideXlab platform.

  • Modeling Supervisory Control in Multi Robot Applications
    2018
    Co-Authors: Mohammadi Raeissi Masoume
    Abstract:

    We consider multi robot applications, where a human operator monitors and supervise the team to pursue complex objectives in complex environments. Robots, specially at field sites, are often subject to unexpected events that can not be managed without the intervention of the operator(s). For example, in an environmental monitoring application, robots might face extreme environmental events (e.g. water currents) or moving obstacles (e.g. animal approaching the robots). In such scenarios, the operator often needs to Interrupt the activities of individual team members to deal with particular situations. This work focuses on human-multi-robot-interaction in these casts. A widely used approach to monitor and supervise robotic teams are team plans, which allow an operator to interact via high level objectives and use automation to work out the details. The first problem we address in this context, is how human Interrupts (i.e. change of action due to unexpected events) can be handled within a robotic team. Typically, after such Interrupts, the operator would need to restart the team plan to ensure its success. This causes delays and imposes extra load on the operator. We address this problem by presenting an approach to encoding how Interrupts can be smoothly handled within a team plan. Building on a team plan formalism that uses Colored Petri Nets, we describe a Mechanism that allows a range of Interrupts to be handled smoothly, allowing the team to effectively continue with its task after the operator intervention. We validate the approach with an application of robotic water monitoring. Our experiments show that the use of our Interrupt Mechanism decreases the time to complete the plan (up to 48% reduction) and decreases the operator load (up to 80% reduction in number of user actions). Moreover, we performed experiments with real robotic platforms to validate the applicability of our Mechanism in the actual deployment of robotic watercraft. The second problem we address is how to handle intervention requests from robots to the operator. In this case, we consider autonomous robotic platforms that are able to identify their situation and ask for the intervention of the operator by sending a request. However, large teams can easily overwhelm the operator with several requests, hence hindering the team performance. As a consequence, team members will have to wait for the operator attention, and the operator becomes a bottleneck for the system. Our contribution in this context is to make the robots learn cooperative strategies to best utilize the operator's time and decrease the idle time of the robotic system. In particular, we consider a queuing model (a.k.a balking queue), where robots decide whether or not to join the queue. Such decisions are computed by considering dynamic features of the system (e.g. the severity of the request, number of requests, etc.). We examine several decision making solutions for computing these cooperative strategies, where our goal is to find a trade-off between lower idle time by joining the queue and fewer failures due to the risk of not joining the queue. We validate the proposed approaches in a simulation robotic water monitoring application. The obtained results show the effectiveness of our proposed models in comparison to the queue without balking, when considering team reward and total idle time

Bruce Jacob - One of the best experts on this subject based on the ideXlab platform.

  • improving the precise Interrupt Mechanism of software managed tlb miss handlers
    IEEE International Conference on High Performance Computing Data and Analytics, 2001
    Co-Authors: Aamer Jaleel, Bruce Jacob
    Abstract:

    The effects of the general-purpose precise Interrupt Mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors handle Interrupts precisely, they typically begin by flushing the pipeline to make the CPU available to execute handler instructions. In doing so, the CPU ends up flushing many instructions that have been brought in to the reorder buffer. In particular, many of these instructions have reached a very deep stage in the pipeline - representing significant work that is wasted. In addition, an overhead of several cycles can be expected in re-fetching and re-executing these instructions. This paper concentrates on improving the performance of precisely handling software managed translation lookaside buffer (TLB) Interrupts, one of the most frequently occurring Interrupts. This paper presents a novel method of in-lining the Interrupt handler within the reorder buffer. Since the first level Interrupt-handlers of TLBs are usually small, they could potentially fit in the reorder buffer along with the user-level code already there. In doing so, the instructions that would otherwise be flushed from the pipe need not be re-fetched and re-executed. Additionally, it allows for instructions independent of the exceptional instruction to continue to execute in parallel with the handler code. We simulate two different schemes of in-lining the Interrupt on a processor with a 4-way out-of-order core similar to the Alpha 21264. We also analyzed the overhead of re-fetching and re-executing instructions when handling an Interrupt by the traditional method. We find that our schemes significantly cut back on the number of instructions being re-fetched by 50-90%, and also provides a performance improvement of 5-25%.

Quaglia Francesco - One of the best experts on this subject based on the ideXlab platform.

  • Time-Sharing Time Warp via Lightweight Operating System Support
    'Association for Computing Machinery (ACM)', 2015
    Co-Authors: Pellegrini Alessandro, Quaglia Francesco
    Abstract:

    The order according to which the different tasks are carried out within a Time Warp platform has a direct impact on performance, given that event processing is speculative, thus being subject to the possibility of being rolled-back. It is typically recognized that not-yet-executed events having lower timestamps should be given higher CPU-schedule priority, since this contributes to keep low the amount of rollbacks. However, common Time Warp platforms usually execute events as atomic actions. Hence control is bounced back to the underlying simulation platform only at the end of the current event processing routine. In other words, CPU-scheduling of events resembles classical batch-multitasking scheduling, which is recognized not to promptly react to variations of the priority of pending tasks (e.g. associated with the injection of new events in the system). In this article we present the design and implementation of a time-sharing Time Warp platform, to be run on multi-core machines, where the platform-level software is allowed to take back control on a periodical basis (with fine grain period), and to possibly preempt any ongoing event processing activity in favor of dispatching (along the same thread) any other event that is revealed to have higher priority. Our proposal is based on an ad-hoc kernel module for Linux, which implements a fine grain timer-Interrupt Mechanism with lightweight management, which is fully integrated with the modern top/bottom-half timer-Interrupt Linux architecture, and which does not induce any bias in terms of relative CPU-usage planning across Time Warp vs non-Time Warp threads running on the machine. Our time-sharing architecture has been integrated within the open source ROOT-Sim optimistic simulation package, and we also report some experimental data for an assessment of our proposal