The Experts below are selected from a list of 285 Experts worldwide ranked by ideXlab platform
Harry Athanassiadis - One of the best experts on this subject based on the ideXlab platform.
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testing interrupts having a service priority order by applying different interrupt priority levels
2001Co-Authors: Harry AthanassiadisAbstract:A test of interrupts in a microprocessor system having a number of interrupt sources which are associated with a memory and assigned a default priority level and a position in a service order. In operation requests for service from the interrupt sources will be processed by calling the interrupt service routine of the interrupt request having the highest priority level or in the event that interrupt requests are at the same priority level are received the interrupt requests will be serviced from first in the service order to last in the service order. The testing mechanism comprises applying an array of priority levels (priority window) to some of the interrupt request lines and enabling all other interrupt requests at their default priority level simultaneously. A value from a global counter is then applied to the memory associated with the interrupt source which is to be serviced. This global counter is then incremented by one and the array of priority values is shifted along the service order from last in the service order to first for successive tests until the test is complete (figure 2b). The values stored in the memories associated with each interrupt source are then compared to a pre-arranged sequence of expected values to determine if an error has occurred in the microprocessor interrupts.
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testing interrupts having a service priority order by applying combinations of interrupt priority levels
2001Co-Authors: Harry AthanassiadisAbstract:A test of interrupts in a microprocessor system having a number of interrupt sources which are associated with a memory and assigned a default priority level and a position in a service order. In operation requests for service from the interrupt sources will be processed by calling the interrupt service routine of the interrupt request having the highest priority level or in the event that interrupt requests are at the same priority level are received the interrupt requests will be serviced from first in the service order to last in the service order. The testing mechanism comprises applying an array of priority levels (priority window, figure 1) except the interrupt having the highest priority to some of the interrupt request lines and enabling all other interrupt requests at their default priority level simultaneously. A value from a global counter is then applied to the memory associated with the interrupt source which is to be serviced. This global counter is then incremented by one and the test is repeated enabling all interrupts simultaneously including the interrupt having the highest priority and the value in the global counter is again applied to the memory of the interrupt to be serviced. Next the array of priority values is shifted along the service order from last in the service order to first according to a sequence for successive tests until all tests have been completed (figure 2b). The values stored in the memories associated with each interrupt source are then compared to a pre-arranged sequence of expected values to determine if an error has occurred in the microprocessor interrupts.
Huajun Wang - One of the best experts on this subject based on the ideXlab platform.
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DSP control implement of Permanent Magnet Synchronous AC servo motor based on vector control
2009 International Conference on Mechatronics and Automation, 2009Co-Authors: Huajun WangAbstract:At present, Permanent Magnet Synchronous Motor (PMSM) AC servo system based on vector control has attracted more and more attentions and the research on it must be a kind of inevitable development trend and focus in the future. This paper is based on DSP TMS320F2812, which is designed for special-purpose on motor control by TI Company, and designs a set of hardware control system for PMSM. The software is written by C2000 assembly language, which realized the speed, current and position loop control. The flow chart of interrupt service routine is available. The simulation results show the excellent performance of DSP control.
Bengt Oelmann - One of the best experts on this subject based on the ideXlab platform.
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Implementing Wireless Sensor Network applications using hierarchical finite state machines
2013 10th IEEE INTERNATIONAL CONFERENCE ON NETWORKING SENSING AND CONTROL (ICNSC), 2013Co-Authors: Matthias Krämer, Sebastian Bader, Bengt OelmannAbstract:In typical application scenarios of wireless sensor systems the embedded software follows a sequential program-flow. Such sequential systems are easily described using a finite state machine (FSM) abstraction model, as it is known from digital circuit design and control system development. In practice, a theoretical description in the form of an FSM must be transferred into a software implementation using an efficient programming abstraction method. This paper presents the implementation of a lightweight software library, which supports the development of wireless sensor applications based on hierarchical finite state machines (HFSM). With its minimalistic design approach, the implementation creates a small memory footprint and a high efficiency in state transitions and in interrupt service routine execution. By introducing a hierarchical state machine architecture it is possible to split a complex algorithm into sub-modules. Hence, the code modularity and reusability is improved. Moreover, it is possible to test each module independently, so that code errors can be traced back more rapidly. This results in a very reliable application software.
Mohd. Shahrizal Rusli - One of the best experts on this subject based on the ideXlab platform.
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Wireless sensor network for smart power management
2009Co-Authors: Mohd. Shahrizal RusliAbstract:Wireless Sensor Network has been widely applied in broad fields in line with current emerging trends, such as automatic control, automated meter reading, power management, etc. Having this system in place provides convenience, increases efficiency and result in well-managed system. The aim of this project is to develop a smart power management system using wireless sensor network. The system is developed by using an unlicensed radio frequency (RF) band where communication takes place between the main controller unit and sensor nodes on the basis of current consumption at every node. Each sensor node will sense current consumption of a dedicated device assigned to it. Data acquisition from the main controller is flexible to operate in round robin or interrupt service routine (ISR) manner. Power consumed by each device which is proportionate to the value measured by the sensor node will be calculated at the main controller and stored in a database within the main controller itself. As many sensor nodes can be placed as possible within the distance range of the main controller (40 meters indoor and 120 meters outdoor line-of-sight). Throughout this project, hardware and software development were done concurrently in order to optimize the time consumption. Validation and verification process includes calibration of current sensor used and experimenting current measurement of several electrical appliances, such as 240V – 12V transformer, electric kettle and hair dryer. Measured device activity can be controlled by placing an electromechanical switch to switch the power ON or OFF.
Chen Zengping - One of the best experts on this subject based on the ideXlab platform.
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the wdm driver development through interrupt service routine
Modern Electronics Technique, 2007Co-Authors: Chen ZengpingAbstract:The real-time performance is one of the difficult points in programming device driver.Focusing on the interrupt working style,this paper discusses the programming mechanism and method of designing and implementing device driver in detail.Then a suite of solution is put forward.Through registering interrupt service routine in OS and applying for an interrupt service thread in the interfacing DLL to wait for invoking,The above two threads are communicated through event handles.When the hardware interrupt is generated,the device driver and the interfacing DLL response individually,then the message sent by interfacing DLL enters the message loop of top-level application.Then the final operation,such as displaying interface and saving data,is performed.With this method a whole interrupt response procedure from base-level device driver to top-level application is completed.The experimental result demonstrates that the design method in this paper owns good effect and practical value,which has realized the integration of least response time and the minimum resource cost.Especially under the circumstances that the average speed can meet the processing demand while the speed of burst of interrupt message exceeds the processing ability of the system,this solution solves the problems of low response speed in traditional design mode and data losing.
