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Deogkyoon Jeong - One of the best experts on this subject based on the ideXlab platform.

  • a 10 gb s 0 03 mm 2 1 28 pj bit half rate all digital injection locked clock and data recovery with maximum timing margin tracking loop
    Asian Solid-State Circuits Conference, 2018
    Co-Authors: Minseong Choo, Sungyong Cho, Kwangho Lee, Deogkyoon Jeong
    Abstract:

    A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit half-rate all-digital injection-locked clock and data recovery (ILCDR) with a path mismatch tracking (PMT) loop is presented. When injection timing is not perfectly matched with the local oscillator, the timing margin of the data sampler is reduced, resulting in the degradation of Jitter Tolerance (JTOL) performance. By simply de-serializing the error information from the phase detector in the conventional phase-locked loop (PLL) based CDR with respect to the polarity of the data transition, the proposed ILCDR achieves robust injection behavior over path mismatch variations. Fabricated in 28-nm CMOS technology, the proposed ILCDR occupies 0.03 mm2 and consumes 12.8 mW at 10 Gb/s with a 0.9-V supply voltage. The measured JTOL is 1 UIpp at 31 MHz with the target bit error rate of 10−12 in the presence of the initial path delay mismatch.

  • a 0 36 pj bit 0 025 mm text 2 12 5 gb s forwarded clock receiver with a stuck free delay locked loop and a half bit delay line in 65 nm cmos technology
    IEEE Transactions on Circuits and Systems, 2016
    Co-Authors: Woorham Bae, Gyu-seob Jeong, Kwanseo Park, Sungyong Cho, Yoonsoo Kim, Deogkyoon Jeong
    Abstract:

    This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the Jitter Tolerance of the FC receiver. In the proposed design, Jitter Tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4- $\text{UI}_{\mathrm{pp}}$ sinusoidal Jitter of 300 MHz.

  • A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
    IEEE Journal of Solid-State Circuits, 2015
    Co-Authors: Gyu-seob Jeong, Sungchun Jang, Deogkyoon Jeong
    Abstract:

    This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional Jitter at the front-end, not only magnitude and bandwidth but also group-delay responses are considered. The AD-CDR employs an LC quadrature digitally controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock Jitter is 1.28 ps rms and the measured Jitter Tolerance exceeds the Tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 for a bit error rate of 10-12 at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm2 and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.

  • a 13 8mw 3 0gb s clock embedded video interface with dll based data recovery circuit
    International Solid-State Circuits Conference, 2011
    Co-Authors: Sungchun Jang, Heesoo Song, Seokmin Ye, Deogkyoon Jeong
    Abstract:

    As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since the conventional intra-panel interfaces with multi-drop configurations, such as RSDS and mini-LVDS, increase the cost of overall systems at high bandwidth, new intrapanel interfaces have been proposed to meet the bandwidth requirement with point-to-point configurations [1–5]. This paper presents a new high-speed video interface that offers significant complexity reduction in the receiver. It is because receivers are integrated in a DDI with relatively slow high-voltage processes, while transmitters in host controllers are implemented with the more advanced deep-submicron processes. Compared to the PLL-based clock recovery circuits in [1–2], the DLL-based data recovery circuit occupies a smaller area with lower power consumption and offers unconditionally stable characteristics along with higher Jitter Tolerance.

  • multi gigabit rate clock and data recovery based on blind oversampling
    IEEE Communications Magazine, 2003
    Co-Authors: Deogkyoon Jeong
    Abstract:

    This article addresses issues with designing a blind oversampling clock and data recovery unit (CDR) that meets Jitter Tolerance specifications. Asymptotic limits on Jitter Tolerance are derived assuming ideal phase detection based on a priori statistics of the received signal, proving that the coarse timing resolution of blind oversampling CDR relies on a phase detection algorithm that makes good estimates of the signal's statistics with a finite number of discrete samples and at reasonable hardware costs. The statistical simulation methodology outlined here enables quick verification of the bit error rate and comparisons between the Jitter Tolerances of various blind oversampling CDR architectures.

Palle Jeppesen - One of the best experts on this subject based on the ideXlab platform.

Hirotaka Tamura - One of the best experts on this subject based on the ideXlab platform.

  • Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs
    IEEE Journal of Solid-State Circuits, 2018
    Co-Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
    Abstract:

    A loop gain adaptation technique is proposed, which optimizes the Jitter Tolerance (JTOL) of a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented in 28 nm CMOS. The technique increases the CDR’s loop gain to suppress the most Jitter while monitoring the autocorrelation function of the bang-bang phase detector (BB-PD) output to prevent the CDR from becoming too underdamped. The proposed technique requires no knowledge of the CDR’s loop latency or input Jitter characteristics.

  • 6 7 a 28gb s digital cdr with adaptive loop gain for optimum Jitter Tolerance
    International Solid-State Circuits Conference, 2017
    Co-Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
    Abstract:

    As we move to higher data rates, the performance of clock and data recovery (CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes their performance sensitive to changes in Jitter caused by PVT variations, crosstalk or power supply noise. This is because the gain of a BB-PD depends on the CDR input Jitter, causing the loop gain of the CDR to change if the Jitter magnitude or spectrum varies. This problem is illustrated in Fig. 6.7.1 where small Jitter leads to excessive loop gain and hence to an underdamped behaviour in the CDR Jitter Tolerance (JTOL), while large Jitter leads to insufficient loop gain and hence to low overall JTOL. To prevent this, we propose a CDR with an adaptive loop gain, K G , as shown in Fig. 6.7.1.

  • Loss Channel Mohammad Sadegh Jalali, Student Member, IEEE,
    2016
    Co-Authors: Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Senior Member, Hirotaka Tamura
    Abstract:

    Abstract—This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3 the baud rate. By moving from 2 to 3 sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Mea-surements from our test chip fabricated in Fujitsu's 65 nm CMOS show a high frequency Jitter Tolerance of 0.25 UIpp for a 5 Gb/s PRBS31 with a 60 FR4 channel. Index Terms—ADC-basedCDR, blind-samplingCDR, clock and data recovery, feed-forward CDR. I

  • A 3x Blind ADC-based CDR
    2015
    Co-Authors: Sadegh M. Jalali, Ali Sheikholeslami, Clifford Ting, Masaya Kibune, Behrooz Abiri, Hirotaka Tamura
    Abstract:

    Abstract—This paper uses a 3-bit ADC to blindly sample the received data at 3x the baud rate to recover the data. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu’s 65nm CMOS show a high frequency Jitter Tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16′ ′ FR4 channel. I

  • A Blind Baud-Rate ADC-Based CDR
    2015
    Co-Authors: Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Senior Member, Hirotaka Tamura
    Abstract:

    Abstract—This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The blind baud-rate operation is made pos-sible by using a 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. The blind samples are interpolated to recover center-of-the-eye samples for a speculative Mueller–Muller PD and a 2-tap DFE operation. A test chip, fabricated in 65-nm CMOS, implements a 10-Gb/s CDR with a measured high-frequency Jitter Tolerance of 0.19UI and 300 ppm of frequency offset. Index Terms—ADC-based clock and data recovery (CDR), all-digital CDR, baud-rate CDR, blind-sampling CDR, Mueller–Muller PD (MMPD). I

A T Clausen - One of the best experts on this subject based on the ideXlab platform.

Ali Sheikholeslami - One of the best experts on this subject based on the ideXlab platform.

  • Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs
    IEEE Journal of Solid-State Circuits, 2018
    Co-Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
    Abstract:

    A loop gain adaptation technique is proposed, which optimizes the Jitter Tolerance (JTOL) of a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented in 28 nm CMOS. The technique increases the CDR’s loop gain to suppress the most Jitter while monitoring the autocorrelation function of the bang-bang phase detector (BB-PD) output to prevent the CDR from becoming too underdamped. The proposed technique requires no knowledge of the CDR’s loop latency or input Jitter characteristics.

  • 6 7 a 28gb s digital cdr with adaptive loop gain for optimum Jitter Tolerance
    International Solid-State Circuits Conference, 2017
    Co-Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
    Abstract:

    As we move to higher data rates, the performance of clock and data recovery (CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes their performance sensitive to changes in Jitter caused by PVT variations, crosstalk or power supply noise. This is because the gain of a BB-PD depends on the CDR input Jitter, causing the loop gain of the CDR to change if the Jitter magnitude or spectrum varies. This problem is illustrated in Fig. 6.7.1 where small Jitter leads to excessive loop gain and hence to an underdamped behaviour in the CDR Jitter Tolerance (JTOL), while large Jitter leads to insufficient loop gain and hence to low overall JTOL. To prevent this, we propose a CDR with an adaptive loop gain, K G , as shown in Fig. 6.7.1.

  • Loss Channel Mohammad Sadegh Jalali, Student Member, IEEE,
    2016
    Co-Authors: Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Senior Member, Hirotaka Tamura
    Abstract:

    Abstract—This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3 the baud rate. By moving from 2 to 3 sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Mea-surements from our test chip fabricated in Fujitsu's 65 nm CMOS show a high frequency Jitter Tolerance of 0.25 UIpp for a 5 Gb/s PRBS31 with a 60 FR4 channel. Index Terms—ADC-basedCDR, blind-samplingCDR, clock and data recovery, feed-forward CDR. I

  • A 3x Blind ADC-based CDR
    2015
    Co-Authors: Sadegh M. Jalali, Ali Sheikholeslami, Clifford Ting, Masaya Kibune, Behrooz Abiri, Hirotaka Tamura
    Abstract:

    Abstract—This paper uses a 3-bit ADC to blindly sample the received data at 3x the baud rate to recover the data. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu’s 65nm CMOS show a high frequency Jitter Tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16′ ′ FR4 channel. I

  • A Blind Baud-Rate ADC-Based CDR
    2015
    Co-Authors: Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Senior Member, Hirotaka Tamura
    Abstract:

    Abstract—This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The blind baud-rate operation is made pos-sible by using a 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. The blind samples are interpolated to recover center-of-the-eye samples for a speculative Mueller–Muller PD and a 2-tap DFE operation. A test chip, fabricated in 65-nm CMOS, implements a 10-Gb/s CDR with a measured high-frequency Jitter Tolerance of 0.19UI and 300 ppm of frequency offset. Index Terms—ADC-based clock and data recovery (CDR), all-digital CDR, baud-rate CDR, blind-sampling CDR, Mueller–Muller PD (MMPD). I