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David Brooks - One of the best experts on this subject based on the ideXlab platform.

  • Energy characterization and instruction Level Energy model of intel s xeon phi processor
    International Symposium on Low Power Electronics and Design, 2013
    Co-Authors: Yakun Sophia Shao, David Brooks
    Abstract:

    Intel's Xeon Phi is the first commercial many-core/multi-thread x86--based processor. Xeon Phi belongs to a new breed of high performance computing processors that seek high compute density as well as Energy efficiency. However, no high-Level Energy model is available for Xeon Phi software developers to quickly evaluate and optimize Energy efficiency. This work demonstrates an instruction-Level Energy model for the Xeon Phi processor to facilitate the development of Energy-efficient software. In order to construct this model, we first characterize the Energy consumption of the processor, identifying how Energy per instruction scales with the number of cores, the number of active threads per core, and instruction types. Based on the Energy characterization, we construct an instruction-Level Energy model and validate the accuracy of the model between 1% and 5% for real world benchmarks. We show that the Energy model can be used to identify software inefficiencies for these benchmarks and find that Linpack code can be optimized to increase Energy efficiency by as much as 10%.

  • ISLPED - Energy characterization and instruction-Level Energy model of Intel's Xeon Phi processor
    International Symposium on Low Power Electronics and Design (ISLPED), 2013
    Co-Authors: Yakun Sophia Shao, David Brooks
    Abstract:

    Intel's Xeon Phi is the first commercial many-core/multi-thread x86--based processor. Xeon Phi belongs to a new breed of high performance computing processors that seek high compute density as well as Energy efficiency. However, no high-Level Energy model is available for Xeon Phi software developers to quickly evaluate and optimize Energy efficiency. This work demonstrates an instruction-Level Energy model for the Xeon Phi processor to facilitate the development of Energy-efficient software. In order to construct this model, we first characterize the Energy consumption of the processor, identifying how Energy per instruction scales with the number of cores, the number of active threads per core, and instruction types. Based on the Energy characterization, we construct an instruction-Level Energy model and validate the accuracy of the model between 1% and 5% for real world benchmarks. We show that the Energy model can be used to identify software inefficiencies for these benchmarks and find that Linpack code can be optimized to increase Energy efficiency by as much as 10%.

C. Chakrabarti - One of the best experts on this subject based on the ideXlab platform.

  • System-Level Energy-efficient dynamic task scheduling
    Proceedings. 42nd Design Automation Conference 2005., 2005
    Co-Authors: Jianli Zhuo, C. Chakrabarti
    Abstract:

    Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor Energy by slowing down the DVS processor and stretching the task execution time. But in a DVS system consisting of a DVS processor and multiple devices, slowing down the processor increases the device Energy consumption and thereby the system-Level Energy consumption. In this paper, we present dynamic task scheduling algorithms for periodic tasks that minimize the system-Level Energy (CPU Energy + device standby Energy). The algorithms use a combination of (i) optimal speed setting, which is the speed that minimizes the system Energy for a specific task, and (ii) limited preemption which reduces the numbers of possible preemptions. For the case when the CPU power and device power are comparable, these algorithms achieve up to 43% Energy savings, but only up to 12% over the non-DVS scheduling. If the device power is large compared to the CPU power, we show that DVS should not be employed.

  • DAC - System-Level Energy-efficient dynamic task scheduling
    Proceedings of the 42nd annual conference on Design automation - DAC '05, 2005
    Co-Authors: Jianli Zhuo, C. Chakrabarti
    Abstract:

    Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor Energy by slowing down the DVS processor and stretching the task execution time. But in a DVS system consisting of a DVS processor and multiple devices, slowing down the processor increases the device Energy consumption and thereby the system-Level Energy consumption. In this paper, we present dynamic task scheduling algorithms for periodic tasks that minimize the system-Level Energy (CPU Energy + device standby Energy). The algorithms use a combination of (i) optimal speed setting, which is the speed that minimizes the system Energy for a specific task, and (ii) limited preemption which reduces the numbers of possible preemptions. For the case when the CPU power and device power are comparable, these algorithms achieve up to 43% Energy savings compared to [1], but only up to 12% over the non-DVS scheduling. If the device power is large compared to the CPU power, we show that DVS should not be employed.

Yakun Sophia Shao - One of the best experts on this subject based on the ideXlab platform.

  • Energy characterization and instruction Level Energy model of intel s xeon phi processor
    International Symposium on Low Power Electronics and Design, 2013
    Co-Authors: Yakun Sophia Shao, David Brooks
    Abstract:

    Intel's Xeon Phi is the first commercial many-core/multi-thread x86--based processor. Xeon Phi belongs to a new breed of high performance computing processors that seek high compute density as well as Energy efficiency. However, no high-Level Energy model is available for Xeon Phi software developers to quickly evaluate and optimize Energy efficiency. This work demonstrates an instruction-Level Energy model for the Xeon Phi processor to facilitate the development of Energy-efficient software. In order to construct this model, we first characterize the Energy consumption of the processor, identifying how Energy per instruction scales with the number of cores, the number of active threads per core, and instruction types. Based on the Energy characterization, we construct an instruction-Level Energy model and validate the accuracy of the model between 1% and 5% for real world benchmarks. We show that the Energy model can be used to identify software inefficiencies for these benchmarks and find that Linpack code can be optimized to increase Energy efficiency by as much as 10%.

  • ISLPED - Energy characterization and instruction-Level Energy model of Intel's Xeon Phi processor
    International Symposium on Low Power Electronics and Design (ISLPED), 2013
    Co-Authors: Yakun Sophia Shao, David Brooks
    Abstract:

    Intel's Xeon Phi is the first commercial many-core/multi-thread x86--based processor. Xeon Phi belongs to a new breed of high performance computing processors that seek high compute density as well as Energy efficiency. However, no high-Level Energy model is available for Xeon Phi software developers to quickly evaluate and optimize Energy efficiency. This work demonstrates an instruction-Level Energy model for the Xeon Phi processor to facilitate the development of Energy-efficient software. In order to construct this model, we first characterize the Energy consumption of the processor, identifying how Energy per instruction scales with the number of cores, the number of active threads per core, and instruction types. Based on the Energy characterization, we construct an instruction-Level Energy model and validate the accuracy of the model between 1% and 5% for real world benchmarks. We show that the Energy model can be used to identify software inefficiencies for these benchmarks and find that Linpack code can be optimized to increase Energy efficiency by as much as 10%.

Muhammad Adeel Pasha - One of the best experts on this subject based on the ideXlab platform.

  • An Improved Model for System-Level Energy Minimization on Real-Time Systems
    2019 IEEE 27th International Symposium on Modeling Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2019
    Co-Authors: Saad Zia Sheikh, Muhammad Adeel Pasha
    Abstract:

    Energy-efficient scheduling has become an essential branch in the evolution of real-time systems due to requirements for reliability and portability. Such scheduling algorithms exploit the varying voltage/frequency capability of a processor to reduce its Energy consumption. However, most of these algorithms assume an inaccurate linear correlation between memory latency and core frequency. To make the matter worse, the inclusion of caches has tarnished the predictability of such systems while also increasing the total Energy consumption. Therefore, improved system and task models are crucial for further progression in this domain. In this paper, we propose improvements to existing models in order to incorporate the above-mentioned complexities. We then propose techniques to minimize core-, cache-and system-Level Energy consumptions. Extensive simulations demonstrate the effectiveness of our approach and the impact each proposed technique has on total Energy consumption of the processor.

C. Polychronopoulos - One of the best experts on this subject based on the ideXlab platform.

  • ISCAS (6) - An analytical, transistor-Level Energy model for SRAM-based caches
    ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
    Co-Authors: N. Bellas, Ibrahim N. Hajj, C. Polychronopoulos
    Abstract:

    In this paper, we present a detailed, transistor-Level Energy model of on-chip caches that use SRAM technology. The Energy estimation is based on the work by by Wilson and Jouppi [1994], in which they propose a timing analysis model for SRAM-based caches. Our model uses runtime information of the cache utilization (number of accesses, number of hits, misses, input statistics etc.) gathered during simulation, as well as complexity and internal cache organization parameters (cache size, block size, associativity, banking etc.).

  • An analytical, transistor-Level Energy model for SRAM-based caches
    1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999
    Co-Authors: N. Bellas, I. Hajj, C. Polychronopoulos
    Abstract:

    In this paper, we present a detailed, transistor-Level Energy model of on-chip caches that use SRAM technology. The Energy estimation is based on the work by by Wilson and Jouppi [1994], in which they propose a timing analysis model for SRAM-based caches. Our model uses runtime information of the cache utilization (number of accesses, number of hits, misses, input statistics etc.) gathered during simulation, as well as complexity and internal cache organization parameters (cache size, block size, associativity, banking etc.).