The Experts below are selected from a list of 240 Experts worldwide ranked by ideXlab platform
Sharad Sinha - One of the best experts on this subject based on the ideXlab platform.
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Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.
arXiv: Distributed Parallel and Cluster Computing, 2019Co-Authors: Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei ZhangAbstract:High-Level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction Level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-Level Source Code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-Level Source Code without running time-consuming register-transfer Level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-Level Source Code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL implementation and design feedback.
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DATE - Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
2019 Design Automation & Test in Europe Conference & Exhibition (DATE), 2019Co-Authors: Jieru Zhao, Tingyuan Liang, Sharad SinhaAbstract:High-Level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction Level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-Level Source Code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-Level Source Code without running time-consuming register-transfer Level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-Level Source Code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL Level implementation and design feedback.
Jieru Zhao - One of the best experts on this subject based on the ideXlab platform.
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Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.
arXiv: Distributed Parallel and Cluster Computing, 2019Co-Authors: Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei ZhangAbstract:High-Level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction Level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-Level Source Code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-Level Source Code without running time-consuming register-transfer Level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-Level Source Code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL implementation and design feedback.
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DATE - Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
2019 Design Automation & Test in Europe Conference & Exhibition (DATE), 2019Co-Authors: Jieru Zhao, Tingyuan Liang, Sharad SinhaAbstract:High-Level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction Level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-Level Source Code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-Level Source Code without running time-consuming register-transfer Level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-Level Source Code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL Level implementation and design feedback.
Charles L A Clarke - One of the best experts on this subject based on the ideXlab platform.
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a comparative evaluation of techniques for syntactic Level Source Code analysis
Asia-Pacific Software Engineering Conference, 2000Co-Authors: Anthony Cox, Charles L A ClarkeAbstract:Many program maintenance tools rely on traditional parsing techniques to obtain syntactic Level models of the Code being maintained. When, for some reason, Code cannot be parsed, software maintainers are forced to fall back on ad hoc tools and techniques, such as grep. As an alternative, hierarchical lexical analysis augmented with simple data structures can be used to extract an approximation of the abstract syntax for a Source file. Experiments indicate that such an approach is feasible and produces results comparable to those obtained using a parser.
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APSEC - A comparative evaluation of techniques for syntactic Level Source Code analysis
Proceedings Seventh Asia-Pacific Software Engeering Conference. APSEC 2000, 1Co-Authors: Anthony Cox, Charles L A ClarkeAbstract:Many program maintenance tools rely on traditional parsing techniques to obtain syntactic Level models of the Code being maintained. When, for some reason, Code cannot be parsed, software maintainers are forced to fall back on ad hoc tools and techniques, such as grep. As an alternative, hierarchical lexical analysis augmented with simple data structures can be used to extract an approximation of the abstract syntax for a Source file. Experiments indicate that such an approach is feasible and produces results comparable to those obtained using a parser.
Joost Visser - One of the best experts on this subject based on the ideXlab platform.
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CSMR - Interpretation of Source Code Clusters in Terms of the ISO/IEC-9126 Maintainability Characteristics
2008 12th European Conference on Software Maintenance and Reengineering, 2008Co-Authors: Yiannis Kanellopoulos, Christos Tjortjis, Ilja Heitlager, Joost VisserAbstract:Clustering is a data mining technique that allows the grouping of data points on the basis of their similarity with respect to multiple dimensions of measurement. It has also been applied in the software engineering domain, in particular to support software quality assessment based on Source Code metrics. Unfortunately, since clusters emerge from metrics at the Source Code Level, it is difficult to interpret the significance of clusters at the Level of the quality of the entire system. In this paper, we propose a method for interpreting Source Code clusters using the ISO/IEC 9126 software product quality model. Several methods have been proposed to perform quantitative assessment of software systems in terms of the quality characteristics defined by ISO/IEC 9126. These methods perform mappings of low-Level Source Code metrics to high-Level quality characteristics by various aggregation and weighting procedures. We applied such a method to obtain quality profiles at various abstraction Levels for each generated Source Code cluster. Subsequently, the plethora of quality profiles obtained is visualized such that conclusions about different quality problems in various clusters can be obtained at a glance.
Irfan Ahmed - One of the best experts on this subject based on the ideXlab platform.
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ISC - Automated Reconstruction of Control Logic for Programmable Logic Controller Forensics.
Lecture Notes in Computer Science, 2019Co-Authors: Syed Ali Qasim, Juan Lopezjr., Irfan AhmedAbstract:This paper presents Similo, an automated scalable framework for control logic forensics in industrial control systems. Similo is designed to investigate denial of engineering operations (DEO) attacks, recently demonstrated to hide malicious control logic in a programmable logic controller (PLC) at field sites from an engineering software (at control center). The network traffic (if captured) contains substantial evidence to investigate DEO attacks including manipulation of control logic. Laddis, a state-of-the-art forensic approach for DEO attacks, is a binary-logic decompiler for the Allen-Bradley’s RSLogix engineering software and MicroLogix 1400 PLC. It is developed with extensive manual reverse engineering effort of the underlying proprietary network protocol and the binary control logic. Unfortunately, Laddis is not scalable and requires similar efforts to extend on other engineering software/PLCs. The proposed solution, Similo, is based on the observation that engineering software of different vendors are equipped with decompilers. Similo is a virtual-PLC framework that integrates the decompilers with their respective (previously-captured) ICS network traffic of control logic. It recovers the binary logic into a high-Level Source Code (of the programming languages defined by IEC 61131-3 standard) automatically. Similo can work with both proprietary/open protocols without requiring protocol specifications and the binary formats of control logic. Thus, it is scalable to different ICS vendors. We evaluate Similo on three PLCs of two ICS vendors, i.e. MicroLogix 1400, MicroLogix 1100, and Modicon M221. These PLCs support proprietary protocols and the control logics written in two programming languages: Ladder Logic and Instruction List. The evaluation results show that Similo can accurately reconstruct a control logic from an ICS network traffic and can be used to investigate the DEO attacks effectively.