The Experts below are selected from a list of 1632 Experts worldwide ranked by ideXlab platform
Wei-kai Cheng - One of the best experts on this subject based on the ideXlab platform.
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Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers
2020 IEEE 38th VLSI Test Symposium (VTS), 2020Co-Authors: Jui-hung Hung, Shih-hsu Huang, Chun-hua Cheng, Wei-kai ChengAbstract:A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of Routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire Routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire Routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire Routing Congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based Routing Congestion constraints.
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VTS - Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers
2020 IEEE 38th VLSI Test Symposium (VTS), 2020Co-Authors: Jui-hung Hung, Shih-hsu Huang, Chun-hua Cheng, Wei-kai ChengAbstract:A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of Routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire Routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire Routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire Routing Congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based Routing Congestion constraints.
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Evaluation of routability-driven macro placement with machine-learning technique
2018 7th International Symposium on Next Generation Electronics (ISNE), 2018Co-Authors: Wei-kai Cheng, Chih-shuan WuAbstract:Macro placement is an important step in floor-plan. Macros' location directly affects the next steps, cells placement and wires Routing. However, it is a time-consuming work to evaluate macro placement's result. To address this problem, we propose an effective evaluation method with machine learning technique. Our methodology predicts HPWL and Routing Congestion after macro placement, rather than after cells placement and global Routing. Therefore, it takes much short time that we can get HPWL and Routing Congestion. Experiment results show that our evaluation is accurate and effective.
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Routability-driven macro placement considering pins location
2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2017Co-Authors: Wen-hsien Chen, Wei-kai ChengAbstract:Development of semiconductor process makes devices have smaller area, lower power, and reduced wire connections. To achieve this purpose, macro placement plays an important role in the design flow. In this paper, we present a routability-driven macro placement algorithm considering pins location to optimized scaled Routing Congestion and macro placement area. By considering pins location, reclassify all macros and program floating border value, we improves Routing Congestion and placement area flexibly. Experimental results show that we can improve the performance effectively by integrating our macro placer with other standard-cell placers, such as NTUplace3, to minimize Routing Congestion with only a little area overhead.
Yih-lang Li - One of the best experts on this subject based on the ideXlab platform.
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DAC - Routing Congestion estimation with real design constraints
Proceedings of the 50th Annual Design Automation Conference on - DAC '13, 2013Co-Authors: Charles J. Alpert, Zhuo Li, Yih-lang Li, Natarajan ViswanathanAbstract:To address the routability issue, Routing Congestion estimators (RCE) become essential in industrial design flow. Recently, several RCEs [1-4] based on global Routing engines are developed, but they typically ignore the effects of Routing on timing so that the identified Routing paths may be overlong and thus impractical. To be aware of the timing issues, our proposed global-Routing-based RCE obeys the layer directive and scenic constraints to respectively limit the Routing layers and the maximum Routing wirelength of the potentially timing-critical nets. To handle the scenic constrains, we propose a novel method based on a relaxation-legalization scheme. Also, because the work in [5] reveals that Congestion ratio is a better indicator than overflow to evaluate routability, this work focuses on minimizing the Congestion ratio rather than overflows. As will be shown, the problem of minimizing Congestion ratio is more complicated than minimizing overflows, so we develop a new rip-up and reRouting scheme to reduce Congestion and further to approach a target Congestion ratio. Moreover, to fit the demands of practical uses, this work presents a control utility to trade off runtime and quality, which is an essential function to an industrial RCE tool. Experiments reveal that the proposed RCE is faster and more accurate than another industrial global-Routing-based RCE.
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Routing Congestion estimation with real design constraints
2013 50th ACM EDAC IEEE Design Automation Conference (DAC), 2013Co-Authors: Charles J. Alpert, Zhuo Li, Yih-lang Li, Natarajan ViswanathanAbstract:To address the routability issue, Routing Congestion estimators (RCE) become essential in industrial design flow. Recently, several RCEs [1-4] based on global Routing engines are developed, but they typically ignore the effects of Routing on timing so that the identified Routing paths may be overlong and thus impractical. To be aware of the timing issues, our proposed global-Routing-based RCE obeys the layer directive and scenic constraints to respectively limit the Routing layers and the maximum Routing wirelength of the potentially timing-critical nets. To handle the scenic constrains, we propose a novel method based on a relaxation-legalization scheme. Also, because the work in [5] reveals that Congestion ratio is a better indicator than overflow to evaluate routability, this work focuses on minimizing the Congestion ratio rather than overflows. As will be shown, the problem of minimizing Congestion ratio is more complicated than minimizing overflows, so we develop a new rip-up and reRouting scheme to reduce Congestion and further to approach a target Congestion ratio. Moreover, to fit the demands of practical uses, this work presents a control utility to trade off runtime and quality, which is an essential function to an industrial RCE tool. Experiments reveal that the proposed RCE is faster and more accurate than another industrial global-Routing-based RCE.
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ICCAD - A fast maze-free Routing Congestion estimator with hybrid unilateral monotonic Routing
Proceedings of the International Conference on Computer-Aided Design - ICCAD '12, 2012Co-Authors: Yih-lang LiAbstract:Considering routability issue in the early stages of VLSI design flow can avoid generating an unroutable design. Several recent routablity-driven placers [8--11] adopt a built-in global router to estimate Routing Congestion. While the routability of the placement solution improves, the performance of these placers degrades. Many of these built-in global router and state-of-the-art academic global routers use maze Routing to seek a detoured path. Although very effective, maze Routing is relatively slower than other Routing algorithms, such as pattern Routing and monotonic Routing algorithms. This work presents two efficient Routing algorithms, called unilateral monotonic Routing and hybrid unilateral monotonic Routing, to replace maze Routing and to realize a highly fast maze-free global router that is suited to act as a built-in Routing Congestion estimator for placers. Experimental results indicate that RCE achieves similar Routing quality when compared with [20], as well as an over 20-fold runtime speedup in large benchmarks.
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A fast maze-free Routing Congestion estimator with hybrid unilateral monotonic Routing
2012 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2012Co-Authors: Yih-lang LiAbstract:Considering routability issue in the early stages of VLSI design flow can avoid generating an unroutable design. Several recent routablity-driven placers [8-11] adopt a built-in global router to estimate Routing Congestion. While the routability of the placement solution improves, the performance of these placers degrades. Many of these built-in global router and state-of-the-art academic global routers use maze Routing to seek a detoured path. Although very effective, maze Routing is relatively slower than other Routing algorithms, such as pattern Routing and monotonic Routing algorithms. This work presents two efficient Routing algorithms, called unilateral monotonic Routing and hybrid unilateral monotonic Routing, to replace maze Routing and to realize a highly fast maze-free global router that is suited to act as a built-in Routing Congestion estimator for placers. Experimental results indicate that RCE achieves similar Routing quality when compared with [20], as well as an over 20-fold runtime speedup in large benchmarks.
Jason Cong - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - Optimizing routability in large-scale mixed-size placement
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013Co-Authors: Jason Cong, Kalliopi Tsota, Bingjun XiaoAbstract:One of the necessary requirements for the placement process is that it should be capable of generating routable solutions. This paper describes a simple but effective method leading to the reduction of the Routing Congestion and the final routed wirelength for large-scale mixed-size designs. In order to reduce Routing Congestion and improve routability, we propose blocking narrow regions on the chip. We also propose dummy-cell insertion inside regions characterized by reduced fixed-macro density. Our placer consists of three major components: (i) narrow channel reduction by performing neighbor-based fixed-macro inflation; (ii) dummy-cell insertion inside large regions with reduced fixed-macro density; and (iii) pre-placement inflation by detecting tangled logic structures in the netlist and minimizing the maximum pin density. We evaluated the quality of our placer using the newly released DAC 2012 routability-driven placement contest designs and we compared our results to the top four teams that participated in the placement contest. The experimental results reveal that our placer improves the routability of the DAC 2012 placement contest designs and effectively reduces the Routing Congestion.
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Optimizing routability in large-scale mixed-size placement
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013Co-Authors: Jason Cong, Kalliopi Tsota, Bingjun XiaoAbstract:One of the necessary requirements for the placement process is that it should be capable of generating routable solutions. This paper describes a simple but effective method leading to the reduction of the Routing Congestion and the final routed wirelength for large-scale mixed-size designs. In order to reduce Routing Congestion and improve routability, we propose blocking narrow regions on the chip. We also propose dummy-cell insertion inside regions characterized by reduced fixed-macro density. Our placer consists of three major components: (i) narrow channel reduction by performing neighbor-based fixed-macro inflation; (ii) dummy-cell insertion inside large regions with reduced fixed-macro density; and (iii) pre-placement inflation by detecting tangled logic structures in the netlist and minimizing the maximum pin density. We evaluated the quality of our placer using the newly released DAC 2012 routability-driven placement contest designs and we compared our results to the top four teams that participated in the placement contest. The experimental results reveal that our placer improves the routability of the DAC 2012 placement contest designs and effectively reduces the Routing Congestion.
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physical hierarchy generation with Routing Congestion control
International Symposium on Physical Design, 2002Co-Authors: Chinchih Chang, Jason CongAbstract:In this paper, we develop a multi-level physical hierarchy generation (mPG) algorithm integrated with fast incremental global Routing for directly updating and optimizing Congestion cost during placement. The fast global Routing is achieved by using a fast two-bend Routing and incremental A-tree algorithm. The Routing Congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is also developed for placing objects with significant size variations. Experimental results show that, compared to Gordian-L , the wire length driven mPG is 3-6.5 times faster and generates slightly better wire length for test circuits larger than 100K cells. Moreover, the Congestion driven mPG improves 50% wiring overflow with 5% larger bounding box wire length but 3-6% shorter Routing wire length measured by graph based A-tree.
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ISPD - Physical hierarchy generation with Routing Congestion control
Proceedings of the 2002 international symposium on Physical design - ISPD '02, 2002Co-Authors: Chinchih Chang, Jason CongAbstract:In this paper, we develop a multi-level physical hierarchy generation (mPG) algorithm integrated with fast incremental global Routing for directly updating and optimizing Congestion cost during placement. The fast global Routing is achieved by using a fast two-bend Routing and incremental A-tree algorithm. The Routing Congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is also developed for placing objects with significant size variations. Experimental results show that, compared to Gordian-L , the wire length driven mPG is 3-6.5 times faster and generates slightly better wire length for test circuits larger than 100K cells. Moreover, the Congestion driven mPG improves 50% wiring overflow with 5% larger bounding box wire length but 3-6% shorter Routing wire length measured by graph based A-tree.
Masato Tatsuoka - One of the best experts on this subject based on the ideXlab platform.
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Wire Congestion aware high level synthesis flow with source code compiler
2018 International Conference on IC Design & Technology (ICICDT), 2018Co-Authors: Masato Tatsuoka, Mineo KanekoAbstract:High level synthesis (HLS) is a source-code-driven Register Transfer Level (RTL) design tool, and the performance of a generated RTL is limited by the description of an input code. In order to break through such kind of limitation and to get a further optimized RTL, the optimization of an input source code is indispensable. Routing Congestion is one of such problems we need to consider the refinement of an input source code. Routing Congestion is, in general, difficult to resolve in HLS due to the lack of physical information. The conventional design flow incorporates logic synthesis and physical synthesis into HLS in order to estimate wire Congestion and to feedback the estimation result to the code modification. In this paper, we propose a HLS flow that performs the code improvements by detecting congested parts without using the information from logic and physical synthesis, and the code re-generation using the source code compiler.
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ICICDT - Wire Congestion aware high level synthesis flow with source code compiler
2018 International Conference on IC Design & Technology (ICICDT), 2018Co-Authors: Masato Tatsuoka, Mineo KanekoAbstract:High level synthesis (HLS) is a source-code-driven Register Transfer Level (RTL) design tool, and the performance of a generated RTL is limited by the description of an input code. In order to break through such kind of limitation and to get a further optimized RTL, the optimization of an input source code is indispensable. Routing Congestion is one of such problems we need to consider the refinement of an input source code. Routing Congestion is, in general, difficult to resolve in HLS due to the lack of physical information. The conventional design flow incorporates logic synthesis and physical synthesis into HLS in order to estimate wire Congestion and to feedback the estimation result to the code modification. In this paper, we propose a HLS flow that performs the code improvements by detecting congested parts without using the information from logic and physical synthesis, and the code re-generation using the source code compiler.
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Physically aware High Level Synthesis design flow
2015 52nd ACM EDAC IEEE Design Automation Conference (DAC), 2015Co-Authors: Masato Tatsuoka, Ryosuke Watanabe, Tatsushi Otsuka, Takashi Hasegawa, Ryosuke Okamura, Xingri Li, Tsuyoshi TakabatakeAbstract:High Level Synthesis (HLS) has many productivity advantages over traditional RTL design, but Routing Congestion is difficult to resolve due to the lack of physical information in HLS. In this paper we propose a novel design flow by integrating a HLS tool with physically aware logic synthesis technology. Using this approach, one can discover Congestion problems early and trace their sources to specific parts of the input SystemC models. This allows designers to resolve the Congestion problems before going to the layout design phase. We applied this flow to a large-scale HLS production design with results showing that this flow can significantly improve not only Routing Congestion but design area and timing as well.
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DAC - Physically aware high level synthesis design flow
Proceedings of the 52nd Annual Design Automation Conference on - DAC '15, 2015Co-Authors: Masato Tatsuoka, Ryosuke Watanabe, Tatsushi Otsuka, Takashi Hasegawa, Ryosuke Okamura, Xingri Li, Tsuyoshi TakabatakeAbstract:High Level Synthesis (HLS) has many productivity advantages over traditional RTL design, but Routing Congestion is difficult to resolve due to the lack of physical information in HLS. In this paper we propose a novel design flow by integrating a HLS tool with physically aware logic synthesis technology. Using this approach, one can discover Congestion problems early and trace their sources to specific parts of the input SystemC models. This allows designers to resolve the Congestion problems before going to the layout design phase. We applied this flow to a large-scale HLS production design with results showing that this flow can significantly improve not only Routing Congestion but design area and timing as well.
Jui-hung Hung - One of the best experts on this subject based on the ideXlab platform.
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Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers
2020 IEEE 38th VLSI Test Symposium (VTS), 2020Co-Authors: Jui-hung Hung, Shih-hsu Huang, Chun-hua Cheng, Wei-kai ChengAbstract:A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of Routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire Routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire Routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire Routing Congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based Routing Congestion constraints.
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VTS - Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers
2020 IEEE 38th VLSI Test Symposium (VTS), 2020Co-Authors: Jui-hung Hung, Shih-hsu Huang, Chun-hua Cheng, Wei-kai ChengAbstract:A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of Routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire Routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire Routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire Routing Congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based Routing Congestion constraints.
