The Experts below are selected from a list of 240 Experts worldwide ranked by ideXlab platform

Shekhar Borkar - One of the best experts on this subject based on the ideXlab platform.

  • area efficient Linear Regulator with ultra fast load regulation
    Symposium on VLSI Circuits, 2005
    Co-Authors: Peter Hazucha, Tanay Karnik, B A Bloechel, C Parsons, D Finan, Shekhar Borkar
    Abstract:

    We demonstrate a fully integrated Linear Regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the Regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small Regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .

  • an area efficient integrated Linear Regulator with ultra fast load regulation
    Symposium on VLSI Circuits, 2004
    Co-Authors: Peter Hazucha, Tanay Karnik, B A Bloechel, C Parsons, D Finan, Shekhar Borkar
    Abstract:

    We demonstrate a fully-integrated Linear Regulator for multi-supply-voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast, single-stage load regulation achieves 0.54 ns response time at 94% current efficiency. This enables 10% peak-to-peak output noise for a 100 mA load step with only a small on-chip decoupling capacitor of 0.6 nF. A PMOS pull-up transistor in the output stage results in a small Regulator area of 0.008 mm/sup 2/ and the 0.6 nF MOS capacitor area of 0.090 mm/sup 2/.

Michael Cantoni - One of the best experts on this subject based on the ideXlab platform.

Peter Hazucha - One of the best experts on this subject based on the ideXlab platform.

  • high voltage tolerant Linear Regulator with fast digital control for biasing of integrated dc dc converters
    International Solid-State Circuits Conference, 2007
    Co-Authors: Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S Gardner, S Rajapandian, Tanay Karnik
    Abstract:

    Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated Linear Regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the Linear Regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, Linear Regulator occupies 0.03 mm2 for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work

  • a Linear Regulator with fast digital control for biasing integrated dc dc converters
    International Solid-State Circuits Conference, 2006
    Co-Authors: Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S Gardner, S Rajapandian, Tanay Karnik
    Abstract:

    A high-voltage-tolerant 2.4 to 1.2V push-pull Linear Regulator with 1A output, 288ps response time, and 97.5% current efficiency for biasing integrated DC-to-DC converters is introduced. The Regulator occupies 0.03mm2 in 90nm CMOS and achieves 33A/mm2 current density. Digital control with a flash ADC and a digital-to-current converter improve speed-power performance by 3times

  • ISSCC - A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters
    2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006
    Co-Authors: Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S Gardner, S Rajapandian, Tanay Karnik
    Abstract:

    A high-voltage-tolerant 2.4 to 1.2V push-pull Linear Regulator with 1A output, 288ps response time, and 97.5% current efficiency for biasing integrated DC-to-DC converters is introduced. The Regulator occupies 0.03mm2 in 90nm CMOS and achieves 33A/mm2 current density. Digital control with a flash ADC and a digital-to-current converter improve speed-power performance by 3times

  • area efficient Linear Regulator with ultra fast load regulation
    Symposium on VLSI Circuits, 2005
    Co-Authors: Peter Hazucha, Tanay Karnik, B A Bloechel, C Parsons, D Finan, Shekhar Borkar
    Abstract:

    We demonstrate a fully integrated Linear Regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the Regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small Regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .

  • an area efficient integrated Linear Regulator with ultra fast load regulation
    Symposium on VLSI Circuits, 2004
    Co-Authors: Peter Hazucha, Tanay Karnik, B A Bloechel, C Parsons, D Finan, Shekhar Borkar
    Abstract:

    We demonstrate a fully-integrated Linear Regulator for multi-supply-voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast, single-stage load regulation achieves 0.54 ns response time at 94% current efficiency. This enables 10% peak-to-peak output noise for a 100 mA load step with only a small on-chip decoupling capacitor of 0.6 nF. A PMOS pull-up transistor in the output stage results in a small Regulator area of 0.008 mm/sup 2/ and the 0.6 nF MOS capacitor area of 0.090 mm/sup 2/.

Peter M. Dower - One of the best experts on this subject based on the ideXlab platform.

  • Game representations for state constrained continuous time Linear Regulator problems
    arXiv: Optimization and Control, 2019
    Co-Authors: Peter M. Dower, William M. Mceneaney, Michael William Cantoni
    Abstract:

    A supremum-of-quadratics representation for convex barrier-type constraints is developed and applied within the context of a class of continuous time state constrained Linear Regulator problems. Using this representation, it is shown that a Linear Regulator problem subjected to such a convex barrier-type constraint can be equivalently formulated as an unconstrained two-player Linear quadratic game. By demonstrating equivalence of the upper and lower values of this game, state feedback characterizations for the optimal policies of both players are developed. These characterizations are subsequently illustrated by example.

  • CDC - A game representation for state constrained Linear Regulator problems
    2016 IEEE 55th Conference on Decision and Control (CDC), 2016
    Co-Authors: Peter M. Dower, William M. Mceneaney, Michael Cantoni
    Abstract:

    A supremum-of-quadratics representation for a class of convex barrier-type constraints is developed and applied in a class of continuous time state constrained Linear Regulator problems. Using this representation, it is shown that any Linear Regulator problem constrained by such a convex barrier-type constraint can be equivalently formulated as an unconstrained two player Linear quadratic game.

  • AuCC - An approximating game for a continuous-time state-constrained Linear Regulator problem
    2016 Australian Control Conference (AuCC), 2016
    Co-Authors: Peter M. Dower, Michael Cantoni
    Abstract:

    A supremum-of-quadratics representation for convex barrier functions is used to approximate a continuous-time state-constrained Linear Regulator problem as a two-player dynamic game. State feedback characterizations for the optimal policies of both players are developed, and subsequently illustrated in a pair of simple examples.

  • a max plus based fundamental solution for a class of discrete time Linear Regulator problems
    Linear Algebra and its Applications, 2015
    Co-Authors: Huan Zhang, Peter M. Dower
    Abstract:

    Abstract Efficient Riccati equation based techniques for the approximate solution of discrete time Linear Regulator problems are restricted in their application to problems with quadratic terminal payoffs. Where non-quadratic terminal payoffs are required, these techniques fail due to the attendant non-quadratic value functions involved. In order to compute these non-quadratic value functions, it is often necessary to appeal directly to dynamic programming in the form of grid- or element-based iterations for the value function. These iterations suffer from poor scalability with respect to problem dimension and time horizon. In this paper, a new max-plus based method is developed for the approximate solution of discrete time Linear Regulator problems with non-quadratic payoffs. This new method is underpinned by the development of new fundamental solutions to such Linear Regulator problems, via max-plus duality. In comparison with a typical grid-based approach, a substantial reduction in computational effort is observed in applying this new max-plus method. A number of simple examples are presented that illustrate this and other observations.

  • A max-plus based fundamental solution for a class of discrete time Linear Regulator problems ☆
    Linear Algebra and its Applications, 2015
    Co-Authors: Huan Zhang, Peter M. Dower
    Abstract:

    Efficient Riccati equation based techniques for the approximate solution of discrete time Linear Regulator problems are restricted in their application to problems with quadratic terminal payoffs. Where non-quadratic terminal payoffs are required, these techniques fail due to the attendant non-quadratic value functions involved. In order to compute these non-quadratic value functions, it is often necessary to appeal directly to dynamic programming in the form of grid- or element-based iterations for the value function. These iterations suffer from poor scalability with respect to problem dimension and time horizon. In this paper, a new max-plus based method is developed for the approximate solution of discrete time Linear Regulator problems with non-quadratic payoffs. This new method is underpinned by the development of new fundamental solutions to such Linear Regulator problems, via max-plus duality. In comparison with a typical grid-based approach, a substantial reduction in computational effort is observed in applying this new max-plus method. A number of simple examples are presented that illustrate this and other observations.Comment: 39 pages, 7 figure

C Parsons - One of the best experts on this subject based on the ideXlab platform.

  • area efficient Linear Regulator with ultra fast load regulation
    Symposium on VLSI Circuits, 2005
    Co-Authors: Peter Hazucha, Tanay Karnik, B A Bloechel, C Parsons, D Finan, Shekhar Borkar
    Abstract:

    We demonstrate a fully integrated Linear Regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the Regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small Regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .

  • an area efficient integrated Linear Regulator with ultra fast load regulation
    Symposium on VLSI Circuits, 2004
    Co-Authors: Peter Hazucha, Tanay Karnik, B A Bloechel, C Parsons, D Finan, Shekhar Borkar
    Abstract:

    We demonstrate a fully-integrated Linear Regulator for multi-supply-voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast, single-stage load regulation achieves 0.54 ns response time at 94% current efficiency. This enables 10% peak-to-peak output noise for a 100 mA load step with only a small on-chip decoupling capacitor of 0.6 nF. A PMOS pull-up transistor in the output stage results in a small Regulator area of 0.008 mm/sup 2/ and the 0.6 nF MOS capacitor area of 0.090 mm/sup 2/.