The Experts below are selected from a list of 291 Experts worldwide ranked by ideXlab platform

H. Shikano - One of the best experts on this subject based on the ideXlab platform.

  • a self controllable voltage level svl Circuit and its low power high speed cmos Circuit applications
    IEEE Journal of Solid-state Circuits, 2003
    Co-Authors: Tadayoshi Enomoto, H. Shikano
    Abstract:

    A self-controllable voltage level (SVL) Circuit which can supply a maximum dc voltage to an active-Load Circuit on request or can decrease the dc voltage supplied to a Load Circuit in standby mode was developed. This SVL Circuit can drastically reduce standby leakage power of CMOS logic Circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such Circuits fitted with SVL Circuits can retain data even in the standby mode. The standby power of an 8-bit 0.13-/spl mu/m CMOS ripple carry adder (RCA) with an on-chip SVL Circuit is 8.2 nW, namely, 4.0% of that of an equivalent conventional adder, while the output signal delay is 786 ps, namely, only 2.3% longer than that of the equivalent conventional adder. Moreover, the standby power of a 512-bit memory cell array incorporating an SVL Circuit for a 0.13-/spl mu/m 512-bit SRAM is 69.1 nW, which is 3.9% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-/spl mu/m SRAM is 285 ps, that is, only 2 ps slower than that of the equivalent SRAM.

  • a self controllable voltage level svl Circuit for low power high speed cmos Circuits
    European Solid-State Circuits Conference, 2002
    Co-Authors: Tadayoshi Enomoto, H. Shikano, T Harada
    Abstract:

    A self-controllable-voltage-level (SVL) Circuit--which can supply a maximum DC voltage to an active-Load Circuit on request or can decrease the DC voltage supplied to a Load Circuit in stand-by mode--was developed. This SVL Circuit can drastically reduce stand-by leakage power of CMOS logic Circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such Circuits fitted with SVL Circuits can retain data even in the standby mode. The stand-by power of an 8-bit, 0.13µm CMOS adder with an on-chip SVL Circuit is 11.7 nW, namely, 4.3% of that of an equivalent conventional adder, while the output signal delay is 790 psec, namely, only 3.8% longer than that of the equivalent conventional adder. Moreover, the stand-by power of a 512-bit memory cell array incorporating an SVL Circuit for a 0.13-µm SRAM is 66.1 nW, 2.3% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-µm SRAM is 285 psec, that is, only 2 psec slower than that of the equivalent SRAM.

  • A dynamically controllable DC/DC level converter and its application to high-speed, low-power Circuits
    2000
    Co-Authors: Tadayoshi Enomoto, H. Shikano, H. Iwata, M. Fujii, Nobuhide Yoshida
    Abstract:

    A new DC/DC level converter has been developed for use in high-speed, low-power Circuits. The level converter can increase the DC voltage which is supplied to an active-Load Circuit on request, or supply a minimal DC voltage to a Load Circuit in the stand-by mode. 32-word register files and 512-bit cache SRAMs were developed using 0.25-µm HEMT technology to examine the effectiveness of the DC/DC level converter in power reduction. Experimental results showed that the power dissipation P of the 32-word register file with on-chip DC/DC level converters was 1.04 W, a reduction to 57.1% of that of an equivalent conventional register file, while the operating frequency fc was 6.42 GHz that is 92.9% of f c for the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters was 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM. The DC/DC level converter technology is also useful in that it reduces P due to subthreshold currents in CMOS and pass-transistor logic Circuits.

Tadayoshi Enomoto - One of the best experts on this subject based on the ideXlab platform.

  • a self controllable voltage level svl Circuit and its low power high speed cmos Circuit applications
    IEEE Journal of Solid-state Circuits, 2003
    Co-Authors: Tadayoshi Enomoto, H. Shikano
    Abstract:

    A self-controllable voltage level (SVL) Circuit which can supply a maximum dc voltage to an active-Load Circuit on request or can decrease the dc voltage supplied to a Load Circuit in standby mode was developed. This SVL Circuit can drastically reduce standby leakage power of CMOS logic Circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such Circuits fitted with SVL Circuits can retain data even in the standby mode. The standby power of an 8-bit 0.13-/spl mu/m CMOS ripple carry adder (RCA) with an on-chip SVL Circuit is 8.2 nW, namely, 4.0% of that of an equivalent conventional adder, while the output signal delay is 786 ps, namely, only 2.3% longer than that of the equivalent conventional adder. Moreover, the standby power of a 512-bit memory cell array incorporating an SVL Circuit for a 0.13-/spl mu/m 512-bit SRAM is 69.1 nW, which is 3.9% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-/spl mu/m SRAM is 285 ps, that is, only 2 ps slower than that of the equivalent SRAM.

  • a self controllable voltage level svl Circuit for low power high speed cmos Circuits
    European Solid-State Circuits Conference, 2002
    Co-Authors: Tadayoshi Enomoto, H. Shikano, T Harada
    Abstract:

    A self-controllable-voltage-level (SVL) Circuit--which can supply a maximum DC voltage to an active-Load Circuit on request or can decrease the DC voltage supplied to a Load Circuit in stand-by mode--was developed. This SVL Circuit can drastically reduce stand-by leakage power of CMOS logic Circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such Circuits fitted with SVL Circuits can retain data even in the standby mode. The stand-by power of an 8-bit, 0.13µm CMOS adder with an on-chip SVL Circuit is 11.7 nW, namely, 4.3% of that of an equivalent conventional adder, while the output signal delay is 790 psec, namely, only 3.8% longer than that of the equivalent conventional adder. Moreover, the stand-by power of a 512-bit memory cell array incorporating an SVL Circuit for a 0.13-µm SRAM is 66.1 nW, 2.3% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-µm SRAM is 285 psec, that is, only 2 psec slower than that of the equivalent SRAM.

  • A dynamically controllable DC/DC level converter and its application to high-speed, low-power Circuits
    2000
    Co-Authors: Tadayoshi Enomoto, H. Shikano, H. Iwata, M. Fujii, Nobuhide Yoshida
    Abstract:

    A new DC/DC level converter has been developed for use in high-speed, low-power Circuits. The level converter can increase the DC voltage which is supplied to an active-Load Circuit on request, or supply a minimal DC voltage to a Load Circuit in the stand-by mode. 32-word register files and 512-bit cache SRAMs were developed using 0.25-µm HEMT technology to examine the effectiveness of the DC/DC level converter in power reduction. Experimental results showed that the power dissipation P of the 32-word register file with on-chip DC/DC level converters was 1.04 W, a reduction to 57.1% of that of an equivalent conventional register file, while the operating frequency fc was 6.42 GHz that is 92.9% of f c for the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters was 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM. The DC/DC level converter technology is also useful in that it reduces P due to subthreshold currents in CMOS and pass-transistor logic Circuits.

Akira Sone - One of the best experts on this subject based on the ideXlab platform.

  • global stabilization of high energy response for a duffing type wideband nonlinear energy harvester via self excitation and entrainment
    Journal of Intelligent Material Systems and Structures, 2013
    Co-Authors: Arata Masuda, Atsuko Senda, Tatsuya Sanada, Akira Sone
    Abstract:

    This article presents a resonance-type vibration energy harvester with a Duffing-type nonlinear oscillator that can perform effectively in a wide frequency range. To mitigate the power-bandwidth trade-off in conventional linear harvesters, the resonance frequency band of the harvester is expanded by introducing a Duffing-type nonlinear oscillator in order to enable the harvester to generate larger electric power in a wider frequency range. Such a nonlinear oscillator, however, can have multiple stable steady-state responses in the resonance band with different levels of regeneration energy. In this study, the principle of self-excitation is utilized to destabilize the solutions, except for the highest energy solution. A Load Circuit with a switch between the conventional Load Circuit and a negative resistance Circuit and the switching control law, which depends on the amplitude of the oscillator’s response, are introduced to impart the self-excitation capability in order to entrain the oscillator with the...

S L Rumyantsev - One of the best experts on this subject based on the ideXlab platform.

  • optical triggering of 4h sic thyristors 18 kv class to high currents in purely inductive Load Circuit
    Semiconductor Science and Technology, 2014
    Co-Authors: Michael E. Levinshtein, Lin Cheng, John W. Palmour, S L Rumyantsev, Tanuj Saxena, M S Shur, Anant K. Agarwal
    Abstract:

    Optical switch-on of a very high voltage (18 kV class) 4H-SiC thyristor with an amplification step (pilot thyristor) to the current Imax = 1225 A is demonstrated using a purely inductive Load and a calibrated air transformer. Increasing the inductance of the transformer primary winding slows down the turn on process. However, the inductance has little effect during the initial stage of the switch-on process when the voltage drop on the thyristor and its internal resistance is high. The results show that a further switch-on current increase can be only achieved by introducing additional amplification steps in the pilot thyristor.

Anant K. Agarwal - One of the best experts on this subject based on the ideXlab platform.