The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
T P - One of the best experts on this subject based on the ideXlab platform.
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why is fe hfo 2 more suitable than pzt or sbt for scaled nonvolatile 1 t Memory Cell a retention perspective
IEEE Electron Device Letters, 2016Co-Authors: Nanbo Gong, T PAbstract:The limited retention time for single-transistor Memory Cell based on ferroelectric-gated field-effect-transistor (FeFET) has prevented the commercialization of its nonvolatile Memory (NVM) option using the commercially available ferroelectric materials, such as strontium bismuth tantalite (SBT) or lead zirconium titanate (PZT), as the gate dielectric. However, the recent advent of the HfO2-based ferroelectric has demonstrated the strong possibility of meeting the NVM requirement of 10-year retention on aggressively scaled FeFETs. This letter will analyze why the retention for HfO2-based ferroelectric (FE–HfO2) is much longer than its PZT or SBT counterparts, based on the two major retention loss mechanisms: depolarization field and charge trapping.
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sonos type flash Memory Cell with metal al _ 2 o _ 3 sin si _ 3 n _ 4 si structure for low voltage high speed program erase operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X.w. Wang, T PAbstract:High-quality Al2O3 and Si3N4 dielectrics synthe- sized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash Memory Cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage erase operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/erase (P/E) operations. We fabricated and investigated NAND flash Memory Cells with metal/Al2O3/SiN/Si3N4/Si struc- ture. The fabricated Cell shows 3.8-V Memory window with P/E conditions of +15 V for 100 µ sa nd−10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V Memory window after ten years. Index Terms—Aluminum oxide, charge trap (CT), flash Memory, metal/Al2O3/SiN/Si3N4/Si (MANNS), silicon nitride, SONOS, TANOS.
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sonos type flash Memory Cell with metal hbox al _ 2 hbox o _ 3 hbox sin hbox si _ 3 hbox n _ 4 hbox si structure for low voltage high speed program erase operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X.w. Wang, T PAbstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash Memory Cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage erase operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/erase (P/E) operations. We fabricated and investigated NAND flash Memory Cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated Cell shows 3.8-V Memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V Memory window after ten years.
Jongho Lee - One of the best experts on this subject based on the ideXlab platform.
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diode type nand flash Memory Cell string having super steep switching slope based on positive feedback
IEEE Transactions on Electron Devices, 2016Co-Authors: Sungmin Joe, Byung-gook Park, Myounggon Kang, Ho-jung Kang, Nagyong Choi, Jongho LeeAbstract:A positive feedback (PF) mechanism was adopted for the first time in the Cell string of a 3-D NAND flash Memory where n + and p + regions are formed on both ends of the string to implement a diode-type Cell string. The body consists of a tube-type poly-Si channel. To generate the PF in the channel during a read operation, a new read operation scheme is proposed. In this paper, the simulator was calibrated in terms of trap density ( $D_{\mathrm {it}})$ of a poly-Si channel extracted from fabricated 3-D NAND flash Memory Cells. By utilizing the PF, a NAND flash Memory Cell in a Cell string has a steep subthreshold swing of <1 mV/decade.
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modeling of v_ rm th shift in nand flash Memory Cell device considering crosstalk and short channel effects
IEEE Transactions on Electron Devices, 2008Co-Authors: Sanggoo Jung, Keun Woo Lee, Kiseog Kim, Seungwoo Shin, Seaungsuk Lee, Gihyun Bae, Jongho LeeAbstract:A threshold-voltage (Vth) shift of sub-100-nm NAND flash-Memory Cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The Vth shift of the NAND flash-Memory Cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between Cells, space between Cells, lightly doped-drain depth, and adjacent-Cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent Cells and short-channel effect. Our model showed an accurate prediction of the Vth shift of NAND flash-Memory array and a good agreement with the data from simulation and measurement.
Takayasu Sakurai - One of the best experts on this subject based on the ideXlab platform.
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90 write power saving sram using sense amplifying Memory Cell
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Kouichi Kanda, H Sadaaki, Takayasu SakuraiAbstract:This paper describes a low-power write scheme which reduces SRAM power by 90% by using seven-transistor sense-amplifying Memory Cells. By reducing the bitline swing to V/sub DD//6 and amplifying the voltage swing by a sense-amplifier structure in a Memory Cell, the charging and discharging component of the power of the bit/data lines is reduced. A 64-kb test chip has been fabricated and correct read/write operation has been verified. It is also shown that the scheme can also have the capability of leakage power reduction with small modifications. Achievable leakage power reduction is estimated to be two orders of magnitude from SPICE simulation results.
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90 write power saving sram using sense amplifying Memory Cell
Symposium on VLSI Circuits, 2002Co-Authors: S Hattori, Takayasu SakuraiAbstract:A low power write scheme is proposed for an SRAM using seven-transistor sense-amplifying Memory Cells, which can save 90% of the power in write cycles when 4M SRAM is assumed. By reducing the bit line swing to 1/6 V/sub DD/ and amplifying the voltage swing by a sense-amplifier structure in a Memory Cell, charging and discharging component of the power of the bit lines is reduced. A 64 Kbit test chip has been fabricated and operation has been verified.
Sun Il Shim - One of the best experts on this subject based on the ideXlab platform.
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sonos type flash Memory Cell with metal al _ 2 o _ 3 sin si _ 3 n _ 4 si structure for low voltage high speed program erase operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X.w. Wang, T PAbstract:High-quality Al2O3 and Si3N4 dielectrics synthe- sized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash Memory Cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage erase operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/erase (P/E) operations. We fabricated and investigated NAND flash Memory Cells with metal/Al2O3/SiN/Si3N4/Si struc- ture. The fabricated Cell shows 3.8-V Memory window with P/E conditions of +15 V for 100 µ sa nd−10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V Memory window after ten years. Index Terms—Aluminum oxide, charge trap (CT), flash Memory, metal/Al2O3/SiN/Si3N4/Si (MANNS), silicon nitride, SONOS, TANOS.
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sonos type flash Memory Cell with metal hbox al _ 2 hbox o _ 3 hbox sin hbox si _ 3 hbox n _ 4 hbox si structure for low voltage high speed program erase operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X.w. Wang, T PAbstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash Memory Cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage erase operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/erase (P/E) operations. We fabricated and investigated NAND flash Memory Cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated Cell shows 3.8-V Memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V Memory window after ten years.
X.w. Wang - One of the best experts on this subject based on the ideXlab platform.
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sonos type flash Memory Cell with metal al _ 2 o _ 3 sin si _ 3 n _ 4 si structure for low voltage high speed program erase operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X.w. Wang, T PAbstract:High-quality Al2O3 and Si3N4 dielectrics synthe- sized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash Memory Cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage erase operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/erase (P/E) operations. We fabricated and investigated NAND flash Memory Cells with metal/Al2O3/SiN/Si3N4/Si struc- ture. The fabricated Cell shows 3.8-V Memory window with P/E conditions of +15 V for 100 µ sa nd−10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V Memory window after ten years. Index Terms—Aluminum oxide, charge trap (CT), flash Memory, metal/Al2O3/SiN/Si3N4/Si (MANNS), silicon nitride, SONOS, TANOS.
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sonos type flash Memory Cell with metal hbox al _ 2 hbox o _ 3 hbox sin hbox si _ 3 hbox n _ 4 hbox si structure for low voltage high speed program erase operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X.w. Wang, T PAbstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash Memory Cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage erase operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/erase (P/E) operations. We fabricated and investigated NAND flash Memory Cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated Cell shows 3.8-V Memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V Memory window after ten years.
