The Experts below are selected from a list of 105342 Experts worldwide ranked by ideXlab platform
Aviral Shrivastava - One of the best experts on this subject based on the ideXlab platform.
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efficient code assignment techniques for Local Memory on software managed multicores
ACM Transactions in Embedded Computing Systems, 2015Co-Authors: Jing Lu, Aviral ShrivastavaAbstract:Scaling the Memory hierarchy is a major challenge when we scale the number of cores in a multicore processor. Software Managed Multicore (SMM) architectures come up as one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a Local scratchpad Memory [Banakar et al. 2002]. As the Local Memory usually is small, large applications cannot be directly executed on it. Code and data of the task mapped to each core need to be managed between global Memory and Local Memory. This article solves the problem of efficiently managing code on an SMM architecture. The primary requirement of generating efficient code assignments is a correct management cost model. In this article, we address this problem by proposing a cost calculation graph. In addition, we develop two heuristics CMSM (Code Mapping for Software Managed multicores) and CMSM_advanced that result in efficient code management execution on the Local scratchpad Memory. Experimental results collected after executing applications from the MiBench suite [Guthaus et al. 2001] demonstrate that merely by adopting the correct management cost calculation, even using previous code assignment schemes, we can improve performance by an average of 12p. Combining the correct management cost model and a more optimized code mapping algorithm together, our heuristics can reduce runtime in more than 80p of the cases, and by up to 20p on our set of benchmarks, compared to the state-of-the-art code assignment approach [Jung et al. 2010]. When compared with Instruction-level Parallelism (ILP) results, CMSM_advanced performs an average of 5p worse. We also simulate the benchmarks on a cache-based system, and find that the code management overhead on SMM core with our code management is much less than Memory latency of a cache-based system.
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a software only scheme for managing heap data on limited Local Memory llm multicore processors
ACM Transactions in Embedded Computing Systems, 2013Co-Authors: Ke Bai, Aviral ShrivastavaAbstract:This article presents a scheme for managing heap data in the Local Memory present in each core of a limited Local Memory (LLM) multicore architecture. Although managing heap data semi-automatically with software cache is feasible, it may require modifications of other thread codes. Crossthread modifications are very difficult to code and debug, and will become more complex and challenging as we increase the number of cores. In this article, we propose an intuitive programming interface, which is an automatic and scalable scheme for heap data management. Besides, for embedded applications, where the maximum heap size can be profiled, we propose several optimizations on our heap management to significantly decrease the library overheads. Our experiments on several benchmarks from MiBench executing on the Sony Playstation 3 show that our scheme is natural to use, and if we know the maximum size of heap data, our optimizations can improve application performance by an average of 14p.
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automatic and efficient heap data management for limited Local Memory multicore architectures
Design Automation and Test in Europe, 2013Co-Authors: Ke Bai, Aviral ShrivastavaAbstract:Limited Local Memory (LLM) multi-core architectures substitute cache with scratch pad memories (SPM), and therefore have much lower power consumption. As they lack of automatic Memory management, programming on such architectures becomes challenging, in the sense that it requires the programmer/compiler to efficiently manage the limited Local Memory. Managing heap data of the tasks executing in the cores of an LLM multi-core is an important problem. This paper presents a fully automated and efficient scheme for heap data management. Specifically, we propose i) code transformation for automation of heap management, with seamless support for multi-level pointers, and ii) improved data structures to more efficiently manage unlimited heap data. Experimental results on several benchmarks from MiBench demonstrate an average 43% performance improvement over previous approach [1].
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stack data management for limited Local Memory llm multi core processors
Application-Specific Systems Architectures and Processors, 2011Co-Authors: Ke Bai, Aviral Shrivastava, Saleel KudchadkerAbstract:Limited Local Memory (LLM) architectures are power-efficient, scalable Memory multi-core architectures, in which cores have a scratch-pad like Local Memory that is software controlled. Any data transfers between the main Memory and the Local Memory must be explicitly present as Direct Memory Access (DMA) commands in the application. Stack data management of the cores is an important problem in LLM architecture, and our previous work outlined a promising scheme for that [1]. In this paper, we improve the previous approach, and now can i) manage limitless stack data, ii) increase the applicability of stack management, and iii) perform stack management with smaller footprint on the Local Memory. We demonstrate these by executing benchmarks from the MiBench suite on the IBM Cell processor.
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heap data management for limited Local Memory llm multi core processors
International Conference on Hardware Software Codesign and System Synthesis, 2010Co-Authors: Ke Bai, Aviral ShrivastavaAbstract:This paper presents a scheme to manage heap data in the Local Memory present in each core of a limited Local Memory (LLM) multi-core processor. While it is possible to manage heap data semi-automatically using software cache, managing heap data of a core through software cache may require changing the code of the other threads. Cross thread modifications are difficult to code and debug, and only become more difficult as we scale the number of cores. We propose a semi-automatic, and scalable scheme for heap data management that hides this complexity in a library with a much natural programming interface. Furthermore, for embedded applications, where the maximum heap size can be known at compile time, we propose optimizations on the heap management to significantly improve the application performance. Experiments on several benchmarks of MiBench executing on the Sony Playstation 3 show that our scheme is easier to use, and if we know the maximum size of heap data, then our optimizations can improve application performance by an average of 14%.
Ke Bai - One of the best experts on this subject based on the ideXlab platform.
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a software only scheme for managing heap data on limited Local Memory llm multicore processors
ACM Transactions in Embedded Computing Systems, 2013Co-Authors: Ke Bai, Aviral ShrivastavaAbstract:This article presents a scheme for managing heap data in the Local Memory present in each core of a limited Local Memory (LLM) multicore architecture. Although managing heap data semi-automatically with software cache is feasible, it may require modifications of other thread codes. Crossthread modifications are very difficult to code and debug, and will become more complex and challenging as we increase the number of cores. In this article, we propose an intuitive programming interface, which is an automatic and scalable scheme for heap data management. Besides, for embedded applications, where the maximum heap size can be profiled, we propose several optimizations on our heap management to significantly decrease the library overheads. Our experiments on several benchmarks from MiBench executing on the Sony Playstation 3 show that our scheme is natural to use, and if we know the maximum size of heap data, our optimizations can improve application performance by an average of 14p.
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automatic and efficient heap data management for limited Local Memory multicore architectures
Design Automation and Test in Europe, 2013Co-Authors: Ke Bai, Aviral ShrivastavaAbstract:Limited Local Memory (LLM) multi-core architectures substitute cache with scratch pad memories (SPM), and therefore have much lower power consumption. As they lack of automatic Memory management, programming on such architectures becomes challenging, in the sense that it requires the programmer/compiler to efficiently manage the limited Local Memory. Managing heap data of the tasks executing in the cores of an LLM multi-core is an important problem. This paper presents a fully automated and efficient scheme for heap data management. Specifically, we propose i) code transformation for automation of heap management, with seamless support for multi-level pointers, and ii) improved data structures to more efficiently manage unlimited heap data. Experimental results on several benchmarks from MiBench demonstrate an average 43% performance improvement over previous approach [1].
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stack data management for limited Local Memory llm multi core processors
Application-Specific Systems Architectures and Processors, 2011Co-Authors: Ke Bai, Aviral Shrivastava, Saleel KudchadkerAbstract:Limited Local Memory (LLM) architectures are power-efficient, scalable Memory multi-core architectures, in which cores have a scratch-pad like Local Memory that is software controlled. Any data transfers between the main Memory and the Local Memory must be explicitly present as Direct Memory Access (DMA) commands in the application. Stack data management of the cores is an important problem in LLM architecture, and our previous work outlined a promising scheme for that [1]. In this paper, we improve the previous approach, and now can i) manage limitless stack data, ii) increase the applicability of stack management, and iii) perform stack management with smaller footprint on the Local Memory. We demonstrate these by executing benchmarks from the MiBench suite on the IBM Cell processor.
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heap data management for limited Local Memory llm multi core processors
International Conference on Hardware Software Codesign and System Synthesis, 2010Co-Authors: Ke Bai, Aviral ShrivastavaAbstract:This paper presents a scheme to manage heap data in the Local Memory present in each core of a limited Local Memory (LLM) multi-core processor. While it is possible to manage heap data semi-automatically using software cache, managing heap data of a core through software cache may require changing the code of the other threads. Cross thread modifications are difficult to code and debug, and only become more difficult as we scale the number of cores. We propose a semi-automatic, and scalable scheme for heap data management that hides this complexity in a library with a much natural programming interface. Furthermore, for embedded applications, where the maximum heap size can be known at compile time, we propose optimizations on the heap management to significantly improve the application performance. Experiments on several benchmarks of MiBench executing on the Sony Playstation 3 show that our scheme is easier to use, and if we know the maximum size of heap data, then our optimizations can improve application performance by an average of 14%.
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dynamic code mapping for limited Local Memory systems
Application-Specific Systems Architectures and Processors, 2010Co-Authors: Seung Chul Jung, Aviral Shrivastava, Ke BaiAbstract:This paper presents heuristics for dynamic management of application code on limited Local memories present in high-performance multi-core processors. Previous techniques formulate the problem using call graphs, which do not capture the temporal ordering of functions. In addition, they only use a conservative estimate of the interference cost between functions to obtain a mapping. As a result previous techniques are unable to achieve efficient code mapping. Techniques proposed in this paper overcome both these limitations and achieve superior code mapping. Experimental results from executing benchmarks from MiBench onto the Cell processor in the Sony Playstation 3 demonstrate up to 29% and average 12% performance improvement, at tolerable compile-time overhead.
Tatsuo Nakajima - One of the best experts on this subject based on the ideXlab platform.
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Monitoring Integrity Using Limited Local Memory
2015Co-Authors: Yuki Kinebuchi, Shakeel Butt, Vinod Ganapathy, Liviu Iftode, Tatsuo NakajimaAbstract:Abstract—System integrity monitors, such as rootkit detectors, rely critically on the ability to fetch and inspect pages containing code and data of a target system under study. To avoid being infected by malicious or compromised targets, state-of-the-art system integrity monitors rely on virtualization technology to set up a tamper-proof execution environment. Consequently, the virtualization infrastructure is part of the trusted computing base. However, modern virtual machine monitors are complex entities, with large code bases that are difficult to verify. In this paper, we present a new machine architecture called limited Local Memory (LLM), which we use to set up an alternative tamper-proof execu-tion environment for system integrity monitors. This architecture builds upon recent trends in multicore chip design to equip each processing core with access to a small, private Memory area. We show that the features of the LLM architecture, combined with a novel secure paging mechanism, suffice to bootstrap a tamper-proof execution environment without support for hard-ware virtualization. We demonstrate the utility of this architecture by building a rootkit detector that leverages the key features of LLM. This rootkit detector can safely inspect a target operating system without itself becoming the victim of infection. Index Terms—Local Memory, multicore, system integrity. I
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hardware assisted reliability enhancement for embedded multi core virtualization design
International Symposium on Object Component Service-Oriented Real-Time Distributed Computing, 2011Co-Authors: Tsung Han Lin, Chen-yi Lee, Hiromasa Shimada, Hitoshi Mitake, Yuki Kinebuchi, Alexandre Courbot, Takushi Morita, Tatsuo NakajimaAbstract:In this paper, we propose a virtualization architecture for the multi-core embedded system to provide more system reliability and security while maintaining the same performance without introducing additional special hardware supports or having to implement complex protection mechanism in the virtualization layer. Virtualization has been widely used in embedded systems, especially in consumer electronics, albeit itself is not a new technique, because there are various needs for both GPOS (General Purpose Operating System) and RTOS (Real Time Operating System). The surge of the multi-core platform in the embedded system also helps the consolidation of the virtualization system for its better performance and lower power consumption. Embedded virtualization design usually uses two kinds of approaches. The first one is to use the traditional VMM, but it is too complicated for use in the embedded environment if there is no additional special hardware support. The other is the use of the micro kernel which imposes a modular design. The guest systems, however, would suffer from considerable amount of modifications because the micro kernel lets the guest systems to run in user space. For some RTOSes and theirs applications originally running in kernel space, it makes this approach more difficult to work because a lot of privileged instructions are used in those codes. To achieve better reliability and keep the virtualization layer design light weighted, a common hardware component adopted in the multi-core embedded processors is used in this work. In the most embedded platforms, vendors provide additional on-chip Local Memory for each physical core and these Local Memory areas are private only to their cores. By taking this Memory architecture's advantage, we can mitigate above-mentioned problems at once. We choose to re-map the virtualization layer's program called SPUMONE, which it runs all its guest systems in kernel space, on the Local Memory. By doing so, it can provide additional reliability and security for the entire system because the SPUMONE's design in a multi-core platform has each instance being installed on a separated processor core which is different from the traditional virtualization layer design and the content of each SPUMONE is inaccessible to each others. We also achieve this goal without bringing any overhead to the overall performance.
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Hardware-assisted reliability enhancement for embedded multi-core virtualization design
Proceedings - 1st International Workshop on Cyber-Physical Systems Networks and Applications CPSNA 2011 Workshop Held During RTCSA 2011, 2011Co-Authors: Tsung Han Lin, Chen-yi Lee, Hiromasa Shimada, Hitoshi Mitake, Yuki Kinebuchi, Tatsuo NakajimaAbstract:In this paper, we propose a virtualization architecture for the multi-core embedded system to provide more sys-tem reliability and security while maintaining the same performance without introducing additional special hardware supports or having to implement complex protection mechanism in the virtualization layer. Embedded virtualization design usually uses two kinds of approaches, traditional VMM and microkernel approaches, but both of them suffer from performance or engineering cost problems. To achieve better reliability and keep the virtualization layer design light weighted, a common hardware component called Local Memory adopted in the multi-core embedded processors is used in this work. By taking this Memory ar-chitecture's advantage, we can mitigate above-mentioned problems at once. We choose to re-map the virtualizationlayer's program called SPUMONE, which it runs all its guest systems in kernel space, on the Local Memory. By doing so, it can provide additional reliability and security for the entire system because the SPUMONE's design in a multi-core platform has each instance being installed on a separated processor core, which is different from the traditional virtualization layer design, and therefore the content of each SPUMONE in the Local Memory is inaccessible to each others.
Yi-jay Lin - One of the best experts on this subject based on the ideXlab platform.
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Generating efficient Local Memory access sequences for coupled subscripts in data-parallel programs
Information Sciences, 2003Co-Authors: Tsung-chuan Huang, Liang-cheng Shiu, Yi-jay LinAbstract:Generating the Local Memory access sequences is an integral part of compiling a data-parallel program into an SPMD code. Most previous research into Local Memory access sequences have focused on one-dimensional arrays distributed with CYCLIC(k) distribution. The Local Memory access sequences for multidimensional arrays with independent subscripts are produced by repeatedly applying the method for one-dimensional arrays. However, the task becomes highly complex when subscripts are coupled such that the subscripts in different dimensions depend on the same loop induction variables. This paper presents an efficient approach to computing the iterations executed on each processor by exploiting repetitive patterns in Memory accesses. Smaller iteration tables than those of Ramanujam [Code generation for complex subscripts in data-parallel programs, in: Z. Li et al. (Eds.), Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, vol. 1366, Springer-Verlag, Berlin, 1998, pp. 49-63] are used, the iteration gap table is not required. The method has been implemented on an IBM SP2. Experimental results demonstrate the efficiency of the proposed method.
Alex Nicolau - One of the best experts on this subject based on the ideXlab platform.
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access pattern based Local Memory customization for low power embedded systems
Design Automation and Test in Europe, 2001Co-Authors: Peter Grun, Nikil Dutt, Alex NicolauAbstract:Memory accesses represent a major bottleneck in embedded systems power and performance. Traditionally, the Local Memory relied on a large cache to store all the variables in the application. However, especially in large real-life applications, different types of data exhibit divergent types of Locality and access patterns, with diverse Locality and bandwidth needs. Traditional caches had to compromise between the different types of Locality required by the access patterns, and trade-off performance against bandwidth requirement. Instead, our approach customizes the Local Memory architecture matching the diverse access patterns and Locality types present in the application, to reduce the main Memory bandwidth requirement, and significantly improve power consumption, without sacrificing performance. Our approach generated an average 30% Memory power reduction without degrading performance on a set of large multimedia/general purpose applications and scientific kernels, over the best traditional cache configuration of similar size, demonstrating the utility of our algorithm.
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Local Memory exploration and optimization in embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999Co-Authors: Preeti Ranjan Panda, Nikil Dutt, Alex NicolauAbstract:Embedded processor-based systems allow for the tailoring of the on-chip Memory architecture based on application specific requirements. We present an analytical strategy for exploring the on-chip Memory architecture for a given application, based on a Memory performance estimation scheme. The analytical technique has the important advantage of enabling a fast evaluation of candidate Memory architectures in the early stages of system design. Many digital signal-processing applications involve array accesses and loop nests that can benefit from such an exploration. Our experiments demonstrate that our estimations closely follow the actual simulated performance at significantly reduced run times.