The Experts below are selected from a list of 119553 Experts worldwide ranked by ideXlab platform
Ramesh Karri - One of the best experts on this subject based on the ideXlab platform.
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interactive presentation Logic Level fault tolerance approaches targeting nanoelectronics plas
Design Automation and Test in Europe, 2007Co-Authors: Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a two-Level Logic form have placed crossbar-based Programmable Logic Arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost.
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DATE - Interactive presentation: Logic Level fault tolerance approaches targeting nanoelectronics PLAs
2007Co-Authors: Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a two-Level Logic form have placed crossbar-based Programmable Logic Arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost.
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Wenjing Rao, Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a two-Level Logic form have placed crossbar-based programmable Logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost
Ingrid Verbauwhede - One of the best experts on this subject based on the ideXlab platform.
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a Logic Level design methodology for a secure dpa resistant asic or fpga implementation
Design Automation and Test in Europe, 2004Co-Authors: Kris Tiri, Ingrid VerbauwhedeAbstract:This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
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securing encryption algorithms against dpa at the Logic Level next generation smart card technology
Cryptographic Hardware and Embedded Systems, 2003Co-Authors: Kris Tiri, Ingrid VerbauwhedeAbstract:This paper describes a design method to secure encryption algorithms against Differential Power Analysis at the Logic Level. The method employs Logic gates with a power consumption, which is independent of the data signals, and therefore the technique removes the foundation for DPA. In a design ex- periment, a fundamental component of the DES algorithm has been imple- mented. Detailed transistor Level simulations show a perfect security whenever the layout parasitics are not taken into account.
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CHES - Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
Lecture Notes in Computer Science, 2003Co-Authors: Kris Tiri, Ingrid VerbauwhedeAbstract:This paper describes a design method to secure encryption algorithms against Differential Power Analysis at the Logic Level. The method employs Logic gates with a power consumption, which is independent of the data signals, and therefore the technique removes the foundation for DPA. In a design ex- periment, a fundamental component of the DES algorithm has been imple- mented. Detailed transistor Level simulations show a perfect security whenever the layout parasitics are not taken into account.
Alex Orailoglu - One of the best experts on this subject based on the ideXlab platform.
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interactive presentation Logic Level fault tolerance approaches targeting nanoelectronics plas
Design Automation and Test in Europe, 2007Co-Authors: Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a two-Level Logic form have placed crossbar-based Programmable Logic Arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost.
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DATE - Interactive presentation: Logic Level fault tolerance approaches targeting nanoelectronics PLAs
2007Co-Authors: Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a two-Level Logic form have placed crossbar-based Programmable Logic Arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost.
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Wenjing Rao, Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a two-Level Logic form have placed crossbar-based programmable Logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost
Kris Tiri - One of the best experts on this subject based on the ideXlab platform.
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a Logic Level design methodology for a secure dpa resistant asic or fpga implementation
Design Automation and Test in Europe, 2004Co-Authors: Kris Tiri, Ingrid VerbauwhedeAbstract:This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
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securing encryption algorithms against dpa at the Logic Level next generation smart card technology
Cryptographic Hardware and Embedded Systems, 2003Co-Authors: Kris Tiri, Ingrid VerbauwhedeAbstract:This paper describes a design method to secure encryption algorithms against Differential Power Analysis at the Logic Level. The method employs Logic gates with a power consumption, which is independent of the data signals, and therefore the technique removes the foundation for DPA. In a design ex- periment, a fundamental component of the DES algorithm has been imple- mented. Detailed transistor Level simulations show a perfect security whenever the layout parasitics are not taken into account.
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CHES - Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
Lecture Notes in Computer Science, 2003Co-Authors: Kris Tiri, Ingrid VerbauwhedeAbstract:This paper describes a design method to secure encryption algorithms against Differential Power Analysis at the Logic Level. The method employs Logic gates with a power consumption, which is independent of the data signals, and therefore the technique removes the foundation for DPA. In a design ex- periment, a fundamental component of the DES algorithm has been imple- mented. Detailed transistor Level simulations show a perfect security whenever the layout parasitics are not taken into account.
Wenjing Rao - One of the best experts on this subject based on the ideXlab platform.
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Wenjing Rao, Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a two-Level Logic form have placed crossbar-based programmable Logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost
