The Experts below are selected from a list of 6966 Experts worldwide ranked by ideXlab platform
Nikhil Junankar - One of the best experts on this subject based on the ideXlab platform.
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parallelizing a sequential Logic Simulator using an optimistic framework based on a global parallel heap event queue an experience and performance report
Workshop on Parallel and Distributed Simulation, 2000Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event Simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial Simulator remained unchanged. Wrapper data structures for the Logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each Logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial Simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event Simulators.
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PADS - Parallelizing a sequential Logic Simulator using an optimistic framework based on a global parallel heap event queue: an experience and performance report
Proceedings Fourteenth Workshop on Parallel and Distributed Simulation, 1Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event Simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial Simulator remained unchanged. Wrapper data structures for the Logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each Logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial Simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event Simulators.
Sushil K Prasad - One of the best experts on this subject based on the ideXlab platform.
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parallelizing a sequential Logic Simulator using an optimistic framework based on a global parallel heap event queue an experience and performance report
Workshop on Parallel and Distributed Simulation, 2000Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event Simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial Simulator remained unchanged. Wrapper data structures for the Logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each Logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial Simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event Simulators.
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PADS - Parallelizing a sequential Logic Simulator using an optimistic framework based on a global parallel heap event queue: an experience and performance report
Proceedings Fourteenth Workshop on Parallel and Distributed Simulation, 1Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event Simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial Simulator remained unchanged. Wrapper data structures for the Logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each Logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial Simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event Simulators.
Carl Tropper - One of the best experts on this subject based on the ideXlab platform.
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xtw a parallel and distributed Logic Simulator
Workshop on Parallel and Distributed Simulation, 2005Co-Authors: Carl TropperAbstract:In this paper, a new event scheduling mechanism XEQ and a new rollback procedure rb-messages are proposed for use in optimistic Logic simulation. We incorporate both of these techniques in a Simulator XTW. XTW groups LPs into clusters, and makes use of a multi-level queue, XEQ, to schedule events in the cluster. XEQ has an O(1) event scheduling time complexity. Our new rollback mechanism replaces the use of anti-messages by an rb-message, and eliminates the need for an output queue at each LP. Experimental comparisons to time warp reveal a superior performance on the part of XTW, while experimental results over large circuits (5-milIion-gate to 25-million-gate) shows XTW scales well with both the size of circuits and the number of processors.
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ASP-DAC - XTW, a parallel and distributed Logic Simulator
Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005Co-Authors: Carl TropperAbstract:In this paper, a new event scheduling mechanism XEQ and a new rollback procedure rb-messages are proposed for use in optimistic Logic simulation. We incorporate both of these techniques in a Simulator XTW. XTW groups LPs into clusters, and makes use of a multi-level queue, XEQ, to schedule events in the cluster. XEQ has an O(1) event scheduling time complexity. Our new rollback mechanism replaces the use of anti-messages by an rb-message, and eliminates the need for an output queue at each LP. Experimental comparisons to Time Warp reveal a superior performance on the part of XTW, while experimental results over large circuits (5-million-gate to 25-million-gate) shows XTW scales well with both the size of circuits and the number of processors.
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PADS - XTW, A Parallel and Distributed Logic Simulator
Workshop on Principles of Advanced and Distributed Simulation (PADS'05), 1Co-Authors: Carl TropperAbstract:In this paper, a new event scheduling mechanism XEQ and a new rollback procedure rb-messages are proposed for use in optimistic Logic simulation. We incorporate both of these techniques in a Simulator XTW. XTW groups LPs into clusters, and makes use of a multi-level queue, XEQ, to schedule events in the cluster. XEQ has an O(1) event scheduling time complexity. Our new rollback mechanism replaces the use of anti-messages by an rb-message, and eliminates the need for an output queue at each LP. Experimental comparisons to time warp reveal a superior performance on the part of XTW, while experimental results over large circuits (5-milIion-gate to 25-million-gate) shows XTW scales well with both the size of circuits and the number of processors.
Munehiro Matsuura - One of the best experts on this subject based on the ideXlab platform.
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a pc based Logic Simulator using a look up table cascade emulator
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2006Co-Authors: Hiroki Nakahara, Tsutomu Sasao, Munehiro MatsuuraAbstract:This paper represents a cycle-based Logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for Logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evaluates the given circuit stored in the memory. The LUT cascade emulator runs on an ordinary PC. This paper also compares the method with a Levelized Compiled Code (LCC) Simulator and a Simulator using a Quasi-Reduced Multi-valued Decision Diagram (QRMDD). Our Simulator is 3.5 to 10.6 times faster than the LCC, and 1.1 to 3.9 times faster than the one using a QRMDD. The simulation setup time is 2.0 to 9.8 times shorter than the LCC. The necessary amount of memory is 1/1.8 to 1/5.5 of the one using a QRMDD.
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a fast Logic Simulator using a look up table cascade emulator
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Hiroki Nakahara, Tsutomu Sasao, Munehiro MatsuuraAbstract:This paper shows a new type of a cycle-based Logic simulation method using a look-up table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascades through BDD (binary decision diagram). Then, it stores LUT data to the memory of an LUT cascade emulator. Next, it generates the C code representing the control circuit of the LUT cascade emulator. And, finally, it converts the C code into the execution code. This method is compared with a levelized compiled code (LCC) Simulator with respect to the simulation time and setup time. Although we used standard PC to simulate the circuit, experimental results show that this method is 12-64 times faster than the LCC.
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A Design Algorithm for Sequential Circuits Using LUT Rings
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2005Co-Authors: Hiroki Nakahara, Tsutomu Sasao, Munehiro MatsuuraAbstract:This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with Logic Simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a Logic Simulator that uses the same amount of memory.
Barak A Cohen - One of the best experts on this subject based on the ideXlab platform.
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A cis-regulatory Logic Simulator
BMC Bioinformatics, 2007Co-Authors: Robert D Zeigler, Jason Gertz, Barak A CohenAbstract:Background A major goal of computational studies of gene regulation is to accurately predict the expression of genes based on the cis-regulatory content of their promoters. The development of computational methods to decode the interactions among cis-regulatory elements has been slow, in part, because it is difficult to know, without extensive experimental validation, whether a particular method identifies the correct cis-regulatory interactions that underlie a given set of expression data. There is an urgent need for test expression data in which the interactions among cis-regulatory sites that produce the data are known. The ability to rapidly generate such data sets would facilitate the development and comparison of computational methods that predict gene expression patterns from promoter sequence. Results We developed a gene expression Simulator which generates expression data using user-defined interactions between cis-regulatory sites. The Simulator can incorporate additive, cooperative, competitive, and synergistic interactions between regulatory elements. Constraints on the spacing, distance, and orientation of regulatory elements and their interactions may also be defined and Gaussian noise can be added to the expression values. The Simulator allows for a data transformation that simulates the sigmoid shape of expression levels from real promoters. We found good agreement between sets of simulated promoters and predicted regulatory modules from real expression data. We present several data sets that may be useful for testing new methodologies for predicting gene expression from promoter sequence. Conclusion We developed a flexible gene expression Simulator that rapidly generates large numbers of simulated promoters and their corresponding transcriptional output based on specified interactions between cis-regulatory sites. When appropriate rule sets are used, the data generated by our Simulator faithfully reproduces experimentally derived data sets. We anticipate that using simulated gene expression data sets will facilitate the direct comparison of computational strategies to predict gene expression from promoter sequence. The source code is available online and as additional material. The test sets are available as additional material.
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A cis-regulatory Logic Simulator.
BMC Bioinformatics, 2007Co-Authors: Robert D Zeigler, Jason Gertz, Barak A CohenAbstract:Background A major goal of computational studies of gene regulation is to accurately predict the expression of genes based on the cis-regulatory content of their promoters. The development of computational methods to decode the interactions among cis-regulatory elements has been slow, in part, because it is difficult to know, without extensive experimental validation, whether a particular method identifies the correct cis-regulatory interactions that underlie a given set of expression data. There is an urgent need for test expression data in which the interactions among cis-regulatory sites that produce the data are known. The ability to rapidly generate such data sets would facilitate the development and comparison of computational methods that predict gene expression patterns from promoter sequence.
