The Experts below are selected from a list of 22146 Experts worldwide ranked by ideXlab platform
Sanggug Lee - One of the best experts on this subject based on the ideXlab platform.
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highly linear cmos Low Noise Amplifier with iip3 boosting technique
International SoC Design Conference, 2008Co-Authors: A Mujeeb, Sigit Yuwono, Jeong Seon Lee, Sanggug LeeAbstract:A High Linear technique for the (CMOS) Low Noise Amplifier (LNA) is presented, the proposed method uses an additional PMOS transistor for IIP3 boosting the third order intermodulation distortion (IMD3) current generated by the CS and CG stages.However, reducing the gain and increasing Noise figure, this technique is applied to achieve the linearity of CMOS LNA using 0.18 mum technology. The LNA achieved +14 dBm IIP3, 12 dB gain, and 1.2 dB NF at 2.4 GHz, consuming 8.2 mA from 1.8 V supply.
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image rejection cmos Low Noise Amplifier design optimization techniques
Radio Frequency Integrated Circuits Symposium, 2005Co-Authors: Trung-kien Nguyen, Gookju Ihm, Choongyul Cha, Sanggug LeeAbstract:This paper reviews and analyzes two reported image-rejection (IR) Low-Noise Amplifier (LNA) design techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous Noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18-mum CMOS technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, Lower than 1.5-dB Noise figure, -5-dBm input-referred third-order intercept point and an IR of 26 dB
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an ultra wideband cmos Low Noise Amplifier for 3 5 ghz uwb system
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Changwan Kim, Hoontae Kim, Minsuk Kang, Phan Tuan Anh, Sanggug LeeAbstract:An ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small Noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB Amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.
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cmos Low Noise Amplifier design optimization techniques
IEEE Transactions on Microwave Theory and Techniques, 2004Co-Authors: Trung-kien Nguyen, Chunghwan Kim, Gookju Ihm, Moonsu Yang, Sanggug LeeAbstract:This paper reviews and analyzes four reported Low-Noise Amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical Noise matching, simultaneous Noise and input matching (SNIM), power-constrained Noise optimization, and power-constrained simultaneous Noise and input matching (PCSNIM) techniques. Very simple and insightful sets of Noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the Noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very Low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the Noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.
Thomas H Lee - One of the best experts on this subject based on the ideXlab platform.
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a 1 5 v 1 5 ghz cmos Low Noise Amplifier
IEEE Journal of Solid-state Circuits, 1997Co-Authors: D K Shaeffer, Thomas H LeeAbstract:A 1.5-GHz Low Noise Amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-/spl mu/m CMOS process. The Amplifier provides a forward gain (S21) of 22 dB with a Noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate Noise in MOS devices.
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a 1 5 v 1 5 ghz cmos Low Noise Amplifier
Symposium on VLSI Circuits, 1996Co-Authors: D K Shaeffer, Thomas H LeeAbstract:A 1.5 GHz Low Noise Amplifier for a Global Positioning System (GPS) receiver has been implemented in a 0.6 /spl mu/m CMOS process. This Amplifier provides a forward gain of 22 dB with a Noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. To the authors' knowledge, this represents the Lowest Noise figure reported to date for a CMOS Amplifier operating above 1 GHz.
D K Shaeffer - One of the best experts on this subject based on the ideXlab platform.
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a 1 5 v 1 5 ghz cmos Low Noise Amplifier
IEEE Journal of Solid-state Circuits, 1997Co-Authors: D K Shaeffer, Thomas H LeeAbstract:A 1.5-GHz Low Noise Amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-/spl mu/m CMOS process. The Amplifier provides a forward gain (S21) of 22 dB with a Noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate Noise in MOS devices.
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a 1 5 v 1 5 ghz cmos Low Noise Amplifier
Symposium on VLSI Circuits, 1996Co-Authors: D K Shaeffer, Thomas H LeeAbstract:A 1.5 GHz Low Noise Amplifier for a Global Positioning System (GPS) receiver has been implemented in a 0.6 /spl mu/m CMOS process. This Amplifier provides a forward gain of 22 dB with a Noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. To the authors' knowledge, this represents the Lowest Noise figure reported to date for a CMOS Amplifier operating above 1 GHz.
Kamran Entesari - One of the best experts on this subject based on the ideXlab platform.
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a millimeter wave 23 32 ghz wideband bicmos Low Noise Amplifier
IEEE Journal of Solid-state Circuits, 2010Co-Authors: Mohamed Elnozahi, E Sanchezsinencio, Kamran EntesariAbstract:This paper presents a 23-32 GHz wideband BiCMOS Low-Noise Amplifier (LNA). The LNA utilizes coupled-resonators to provide a wideband load. To our knowledge, the proposed LNA achieves the widest bandwidth with minimum power consumption using 0.18 ?m BiCMOS technology in K-band. Analytical expressions for the wideband input matching, gain, Noise figure and linearity are presented. The LNA is implemented using 0.18 ?m BiCMOS technology and occupies an area of 0.25 mm2 . It achieves a voltage gain of 12 dB, 3-dB bandwidth of 9 GHz, Noise figure between 4.5-6.3 dB, linearity higher than -6.4 dBm with a power consumption of 13 mW from a 1.5 V supply.
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a cmos Low Noise Amplifier with reconfigurable input matching network
IEEE Transactions on Microwave Theory and Techniques, 2009Co-Authors: Mohamed Elnozahi, E Sanchezsinencio, Kamran EntesariAbstract:A reconfigurable Low-Noise Amplifier (LNA) with tunable input matching network is proposed. The tunable input matching network provides continuous tuning of the input resonant circuit. The LNA is implemented using 0.13-mum CMOS technology. The Amplifier has a tuning range of 1.9-2.4 GHz with an input return loss better than -13 dB. The LNA has a measured voltage gain of 10-14 dB and a Noise figure of 3.2-3.7 dB within the band. The LNA consumes 14 mA from a 1.2-V supply. The detailed analysis of the proposed LNA, including the tuning range and additional Noise of the proposed reconfigurable input matching network, is presented. To our knowledge, this is the first architecture that provides continuous tuning of the input matching network.
Chirn Chye Boon - One of the best experts on this subject based on the ideXlab platform.
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an 88 5 110 ghz cmos Low Noise Amplifier for millimeter wave imaging applications
IEEE Microwave and Wireless Components Letters, 2016Co-Authors: Guangyin Feng, Chirn Chye Boon, Fanyi MengAbstract:This letter presents a wideband millimeter-wave Low-Noise Amplifier (LNA) in a 65 nm CMOS technology. The Amplifier adopts five-stage cascode topology with L-type input matching and T-type output matching. By distributing the peak gains of first four stages at two frequency points, the LNA achieves a flat gain response over a wide bandwidth. The measurement results show that the Amplifier features a peak gain of 16.7 dB at 104 GHz, a minimum NF of 7.2 dB, and a 3 dB bandwidth of 21.5 GHz. The LNA consumes 48.6 mW and occupies a compact core area of 0.05 $\text{mm}^{2}$ .
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A wideband Low power Low-Noise Amplifier in CMOS technology
IEEE Transactions on Circuits and Systems I: Regular Papers, 2010Co-Authors: Ali Meaamar, Kiat-seng Yeo, Chirn Chye Boon, Manh Anh DoAbstract:A T-coil network can be implemented as a high order filter for bandwidth extension. This technique is incorporated into the design of the input matching and output peaking networks of a Low-Noise Amplifier. The intrinsic capacitances within the transistors are exploited as a part of the wideband structure to extend the bandwidth. Using the proposed topology, a wideband Low-Noise Amplifier with a bandwidth of 3-8 GHz, a maximum gain of 16.4 dB and Noise figure of 2.9 dB (min) is achieved. The total power consumption of the wideband Low-Noise Amplifier from the 1.8 V power supply is 3.9 mW. The prototype is fabricated in 0.18 ??m CMOS technology.
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a subthreshold Low Noise Amplifier optimized for ultra Low power applications in the ism band
IEEE Transactions on Microwave Theory and Techniques, 2008Co-Authors: Chirn Chye Boon, Kiat-seng Yeo, A CabukAbstract:The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-Low-power design. A subthreshold biased Low-Noise Amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard Low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S11 of -19 dB while using 630 muA of dc current. The measured Noise figure is 5.2 dB.
