The Experts below are selected from a list of 29316 Experts worldwide ranked by ideXlab platform
Mathieu Luisier - One of the best experts on this subject based on the ideXlab platform.
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ab initio simulation of van der waals mote 2 sns 2 heterotunneling fets for Low Power Electronics
IEEE Electron Device Letters, 2015Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in Low-Power Electronics.
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Ab-Initio Simulation of van der Waals MoTe 2 –SnS 2 Heterotunneling FETs for Low-Power Electronics
IEEE Electron Device Letters, 2015Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in Low-Power Electronics.
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Metal-dichalcogenide hetero-TFETs: Are they a viable option for Low Power Electronics?
72nd Device Research Conference, 2014Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Through advanced device simulations, we have demonstrated the feasibility of broken gap heteroTFETs based on strained WTe 2 -MoS 2 . The combination of two tunneling path ensures a Low average iSS and a relatively high ON-current. To improve this performance and move towards Low Power Electronics, other material combinations such as MoTe 2 -SnSe 2 or WSe 2 -SnSe 2 should be investigated with stress as additional design parameter.
Aron Szabo - One of the best experts on this subject based on the ideXlab platform.
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ab initio simulation of van der waals mote 2 sns 2 heterotunneling fets for Low Power Electronics
IEEE Electron Device Letters, 2015Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in Low-Power Electronics.
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Ab-Initio Simulation of van der Waals MoTe 2 –SnS 2 Heterotunneling FETs for Low-Power Electronics
IEEE Electron Device Letters, 2015Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in Low-Power Electronics.
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Metal-dichalcogenide hetero-TFETs: Are they a viable option for Low Power Electronics?
72nd Device Research Conference, 2014Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Through advanced device simulations, we have demonstrated the feasibility of broken gap heteroTFETs based on strained WTe 2 -MoS 2 . The combination of two tunneling path ensures a Low average iSS and a relatively high ON-current. To improve this performance and move towards Low Power Electronics, other material combinations such as MoTe 2 -SnSe 2 or WSe 2 -SnSe 2 should be investigated with stress as additional design parameter.
Steven J. Koester - One of the best experts on this subject based on the ideXlab platform.
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ab initio simulation of van der waals mote 2 sns 2 heterotunneling fets for Low Power Electronics
IEEE Electron Device Letters, 2015Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in Low-Power Electronics.
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Ab-Initio Simulation of van der Waals MoTe 2 –SnS 2 Heterotunneling FETs for Low-Power Electronics
IEEE Electron Device Letters, 2015Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in Low-Power Electronics.
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Metal-dichalcogenide hetero-TFETs: Are they a viable option for Low Power Electronics?
72nd Device Research Conference, 2014Co-Authors: Aron Szabo, Steven J. Koester, Mathieu LuisierAbstract:Through advanced device simulations, we have demonstrated the feasibility of broken gap heteroTFETs based on strained WTe 2 -MoS 2 . The combination of two tunneling path ensures a Low average iSS and a relatively high ON-current. To improve this performance and move towards Low Power Electronics, other material combinations such as MoTe 2 -SnSe 2 or WSe 2 -SnSe 2 should be investigated with stress as additional design parameter.
W.c.b. Peatman - One of the best experts on this subject based on the ideXlab platform.
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Heterodimensional technology for ultra Low Power Electronics
Future Trends in Microelectronics, 1996Co-Authors: W.c.b. Peatman, M. Hurt, Trond Ytterdal, R. Tsai, H. Park, J. Gonzales, Michael S. ShurAbstract:We describe new heterodimensional technology suitable for ultra Low Power applications. This technology uses Schottky barrier contacts between three-dimensional metal and two-dimensional electron gas. The Low Power performance is due to the folLowing: the small capacitance of the 2D-3D junction; the concentration of the depletion layer electric field streamlines in the active channel; suppression of parasitic resistance; small leakage current; and, most of all, due to the total elimination of the narrow channel effect which alLows us to scale the device width to submicron dimensions. We present, compare, and discuss measured and simulated I-V and C-V characteristics for the 2D-3D Schottky diode, 2D MESFET and Schottky Gated 2D-3D RTT.
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Complementary 2-D MESFET for Low Power Electronics. Phase 1.
1995Co-Authors: W.c.b. PeatmanAbstract:Abstract : The purpose of this project was to determine the feasibility of developing a p-channel 2-D MESFET for future Low Power complementary IC technologies. The project demonstrated the fabrication of prototype p-channel 2-D MESFETs having promising electrical characteristics, developed a p-channel 2-D MESFET device model which was implemented into a commercially available SPICE program, demonstrated the SPICE simulation of p-channel 2-D MESFET device characteristics as well as complementary 2-D MESFET circuits, and demonstrated that the complementary 2-D MESFET should have significantly Lower Power-delay product compared with existing technologies. Finally, the project evaluated the manufacturability and technology insertion issues of the new technology. jg p.1
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Complementary 2-D MESFET for Low Power Electronics
1995Co-Authors: W.c.b. PeatmanAbstract:Abstract : The project has four major tasks. These are (1) assessment of the p-channel 2-D MESFET device fabrication, (2) development of a p-channel 2-D MESFET model and implementation of the model into AIM-SPICE, (3) circuit simulations of complementary 2-D MESFET circuits using AIM-SPICE and comparison with conventional circuits, and, (4) analysis of manufacturability and technology insertion issues.
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Novel field effect transistors for Low Power Electronics
1995Co-Authors: W.c.b. PeatmanAbstract:Abstract : The primary objective of this Phase I project was to determine the extent of the significant reduction in Power consumption of integrated circuits which may be achieved by utilizing a novel sidegate FET technology. The new FET technology eliminates the Narrow Channel Effect (NCE) which is one of the primary factors limiting the minimum Power consumption of integrated circuits. By eliminating the NCE, we may scale the device size dramatically and reduce the Power-delay product by at least an order of magnitude compared to existing transistor technologies. Additionally, the new FET has two gates which can therefore lead to a significant reduction in the transistor count of ICs, as was demonstrated in a simple NOR gate using only two transistors. Finally, the transistor technology is compatible with fiFET circuits for microwave/digital applications. In this Phase I project, the design, fabrication, characterization and modeling of the new transistor was investigated and issues concerning manufacturability were discussed.
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Narrow channel 2-D MESFET for Low Power Electronics
IEEE Transactions on Electron Devices, 1995Co-Authors: W.c.b. Peatman, M. Hurt, Hyunchang Park, Trond Ytterdal, R. Tsai, Michael S. ShurAbstract:A 2-D MESFET utilizing sidewall Schottky contacts on either side of a very narrow 2-d electron gas channel is described. Record transconductance of 295 and 130 mS/mm have been achieved at room temperature in 1.0 and 0.5 micron wide devices, respectively. We also present accurate 2-D MESFET current-voltage and capacitance-voltage models. These models have been implemented into AIM-Spice which was used to simulate DCFL inverter and ring oscillator circuits. The ring oscillator simulations predict a Power-delay product of less than 0.1 fJ/gate at room temperature, suggesting that the 2-D MESFET may be useful for ultra Low Power Electronics applications. >
Michael S. Shur - One of the best experts on this subject based on the ideXlab platform.
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Heterodimensional technology for ultra Low Power Electronics
Future Trends in Microelectronics, 1996Co-Authors: W.c.b. Peatman, M. Hurt, Trond Ytterdal, R. Tsai, H. Park, J. Gonzales, Michael S. ShurAbstract:We describe new heterodimensional technology suitable for ultra Low Power applications. This technology uses Schottky barrier contacts between three-dimensional metal and two-dimensional electron gas. The Low Power performance is due to the folLowing: the small capacitance of the 2D-3D junction; the concentration of the depletion layer electric field streamlines in the active channel; suppression of parasitic resistance; small leakage current; and, most of all, due to the total elimination of the narrow channel effect which alLows us to scale the device width to submicron dimensions. We present, compare, and discuss measured and simulated I-V and C-V characteristics for the 2D-3D Schottky diode, 2D MESFET and Schottky Gated 2D-3D RTT.
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Narrow channel 2-D MESFET for Low Power Electronics
IEEE Transactions on Electron Devices, 1995Co-Authors: W.c.b. Peatman, M. Hurt, Hyunchang Park, Trond Ytterdal, R. Tsai, Michael S. ShurAbstract:A 2-D MESFET utilizing sidewall Schottky contacts on either side of a very narrow 2-d electron gas channel is described. Record transconductance of 295 and 130 mS/mm have been achieved at room temperature in 1.0 and 0.5 micron wide devices, respectively. We also present accurate 2-D MESFET current-voltage and capacitance-voltage models. These models have been implemented into AIM-Spice which was used to simulate DCFL inverter and ring oscillator circuits. The ring oscillator simulations predict a Power-delay product of less than 0.1 fJ/gate at room temperature, suggesting that the 2-D MESFET may be useful for ultra Low Power Electronics applications. >
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Heterodimensional MESFETs for ultra Low Power Electronics
1997 Advanced Workshop on Frontiers in Electronics WOFE '97 Proceedings, 1Co-Authors: Trond Ytterdal, W.c.b. Peatman, Michael S. Shur, M. HurtAbstract:Revolutionary change in Electronics technology will be required to meet the pressing need to dramatically reduce the Power consumption of large scale integrated circuits in future Low Power applications such as wireless communications and other portable Electronics. Our approach for realizing such change is to utilize novel two-dimensional metal-semiconductor field effect transistors (2-D MESFETs), which not only can be scaled to deep sub-micron dimensions without suffering severe narrow channel and short channel effects, but also offer new ways to implement basic logic functions using far fewer transistors than are currently required. In addition to Lower Power consumption and greater functionality, these new architectures should dramatically simplify the design process and alLow much denser packing. In this paper we present the heterodimensional technology in general and in particular the 2D MESFET which is one of the devices based on this technology. Furthermore, we explore the advantages of utilizing this device in an integrated circuit environment.
