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Visvesh S Sathe - One of the best experts on this subject based on the ideXlab platform.

  • VLSI Circuits - UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS
    2020 IEEE Symposium on VLSI Circuits, 2020
    Co-Authors: Xun Sun, Rajesh Pamula, Akshat Boora, Chi-hsiang Huang, Diego Pena-colaiocco, Visvesh S Sathe
    Abstract:

    A new and improved Unified Clock and Power (UniCaP) architecture relies on dual-path feedback to further reduce supply-voltage (V dd ) margins in an ARM Cortex M0 Processor while minimizing both peak cycle loss (Δϕ max ) and cycle-loss recovery time (T recovery ) associated with adaptive clocking. Measurements on a 65nm test chip demonstrate 91–99% V dd margin reduction and 38X T recovery improvement over [3]. We also report measurements that quantify the impact of clock distribution delay (τ dist ) and V dd sensitivity on V dd margin reduction.

  • An All-Digital Fused PLL-Buck Architecture for 82% Average V dd -Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • an all digital fused pll buck architecture for 82 average v dd margin reduction in a 0 6 to 1 0 v cortex M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • a unified clock and switched capacitor based power delivery architecture for variation tolerance in low voltage soc domains
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Fahim Ur Rahman, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Xi Li, Visvesh S Sathe
    Abstract:

    Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade Processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and $V_{\mathrm{ dd}}$ variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required $V_{\mathrm{ dd}}$ guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 Processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive $V_{\mathrm{ dd}}$ margin reduction, and continuous $V_{\mathrm{ dd}}$ scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% $V_{\mathrm{ dd}}$ reduction corresponding to a 94% $V_{\mathrm{ dd}}$ margin recovery or an equivalent $3.2\times $ increase in the operating clock frequency ( $f_{\mathrm{ clk}}$ ).

  • an all digital unified clock frequency and switched capacitor voltage regulator for variation tolerance in a sub threshold arm cortex M0 Processor
    Symposium on VLSI Circuits, 2018
    Co-Authors: Fahim Ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Visvesh S Sathe
    Abstract:

    An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 Processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

Fahim Ur Rahman - One of the best experts on this subject based on the ideXlab platform.

  • An All-Digital Fused PLL-Buck Architecture for 82% Average V dd -Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • an all digital fused pll buck architecture for 82 average v dd margin reduction in a 0 6 to 1 0 v cortex M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • a unified clock and switched capacitor based power delivery architecture for variation tolerance in low voltage soc domains
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Fahim Ur Rahman, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Xi Li, Visvesh S Sathe
    Abstract:

    Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade Processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and $V_{\mathrm{ dd}}$ variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required $V_{\mathrm{ dd}}$ guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 Processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive $V_{\mathrm{ dd}}$ margin reduction, and continuous $V_{\mathrm{ dd}}$ scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% $V_{\mathrm{ dd}}$ reduction corresponding to a 94% $V_{\mathrm{ dd}}$ margin recovery or an equivalent $3.2\times $ increase in the operating clock frequency ( $f_{\mathrm{ clk}}$ ).

  • an all digital unified clock frequency and switched capacitor voltage regulator for variation tolerance in a sub threshold arm cortex M0 Processor
    Symposium on VLSI Circuits, 2018
    Co-Authors: Fahim Ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Visvesh S Sathe
    Abstract:

    An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 Processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

  • VLSI Circuits - An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor
    2018 IEEE Symposium on VLSI Circuits, 2018
    Co-Authors: Fahim Ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Visvesh S Sathe
    Abstract:

    An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 Processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

Joseph Yiu - One of the best experts on this subject based on the ideXlab platform.

  • The Definitive Guide to ARM Cortex -M0 and Cortex-M0+ Processors
    2015
    Co-Authors: Joseph Yiu
    Abstract:

    The Definitive Guide to the ARM Cortex-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARMs Cortex-M0 and Cortex-M0+ Processors and their programming techniques. Written by ARMs Senior Embedded Technology Manager, Joseph Yiu, the book is packed with examples on how to use the features in the Cortex-M0 and Cortex-M0+ Processors. It provides detailed information on the instruction set architecture, how to use a number of popular development suites, an overview of the software development flow, and information on how to locate problems in the program code and software porting. This new edition includes the differences between the Cortex-M0 and Cortex-M0+ Processors such as architectural features (e.g. unprivileged execution level, vector table relocation), new chapters on low power designs and the Memory Protection Unit (MPU), the benefits of the Cortex-M0+ Processor, such as the new single cycle I/O interface, higher energy efficiency, better performance and the Micro Trace Buffer (MTB) feature, updated software development tools, updated Real Time Operating System examples using Keil RTX with CMSIS-RTOS APIs, examples of using various Cortex-M0 and Cortex-M0+ based microcontrollers, and much more.Provides detailed information on ARM Cortex-M0 and Cortex-M0+ Processors, including their architectures, programming model, instruction set, and interrupt handlingPresents detailed information on the differences between the Cortex-M0 and Cortex-M0+ ProcessorsCovers software development flow, including examples for various development tools in both C and assembly languagesIncludes in-depth coverage of design approaches and considerations for developing ultra low power embedded systems, the benchmark for energy efficiency in microcontrollers, and examples of utilizing low power features in microcontrollers

  • Memory Protection Unit
    The Definitive Guide to Arm® Cortex®-M0 and Cortex-M0+ Processors, 2015
    Co-Authors: Joseph Yiu
    Abstract:

    This chapter introduces the Memory Protection Unit (MPU), an optional programmable unit in the Cortex ® -M0+ Processor, including its usages, the programmer's model, the configuration steps, and the differences between the MPU in ARMv6-M and ARMv7-M Processors.

  • Chapter 10 – Operating System Support Features
    The Definitive Guide to Arm® Cortex®-M0 and Cortex-M0+ Processors, 2015
    Co-Authors: Joseph Yiu
    Abstract:

    This chapter covers an overview of the features in the Cortex®-M0 and Cortex-M0+ Processor for Operating System support, then move on to the details of these features including the SysTick timer, the banked stack pointer, SVCall and PendSV exceptions, and how context switching works in a Cortex-M Processor with program examples.

  • Chapter 13 – Debug Features
    The Definitive Guide to Arm® Cortex®-M0 and Cortex-M0+ Processors, 2015
    Co-Authors: Joseph Yiu
    Abstract:

    This chapter introduces the debug features of the Cortex®-M0 and Cortex-M0+ Processors. The topics include the debug communication protocols, the debug components inside the Processors, debug events, and an introduction of the Micro Trace Buffer, which provide instruction trace on the Cortex-M0+ Processor.

  • Chapter 2 – Technical Overview
    The Definitive Guide to Arm® Cortex®-M0 and Cortex-M0+ Processors, 2015
    Co-Authors: Joseph Yiu
    Abstract:

    This chapter covers overview of the technical details of ARM® Cortex®-M0 and Cortex-M0+ Processor, examples of how they are integrated into a system, the applications, and various factors for using Cortex-M0 and Cortex-M0+ Processors including details of technical advantages.

Naveen John - One of the best experts on this subject based on the ideXlab platform.

  • An All-Digital Fused PLL-Buck Architecture for 82% Average V dd -Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • an all digital fused pll buck architecture for 82 average v dd margin reduction in a 0 6 to 1 0 v cortex M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • a unified clock and switched capacitor based power delivery architecture for variation tolerance in low voltage soc domains
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Fahim Ur Rahman, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Xi Li, Visvesh S Sathe
    Abstract:

    Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade Processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and $V_{\mathrm{ dd}}$ variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required $V_{\mathrm{ dd}}$ guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 Processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive $V_{\mathrm{ dd}}$ margin reduction, and continuous $V_{\mathrm{ dd}}$ scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% $V_{\mathrm{ dd}}$ reduction corresponding to a 94% $V_{\mathrm{ dd}}$ margin recovery or an equivalent $3.2\times $ increase in the operating clock frequency ( $f_{\mathrm{ clk}}$ ).

  • an all digital unified clock frequency and switched capacitor voltage regulator for variation tolerance in a sub threshold arm cortex M0 Processor
    Symposium on VLSI Circuits, 2018
    Co-Authors: Fahim Ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Visvesh S Sathe
    Abstract:

    An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 Processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

  • VLSI Circuits - An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor
    2018 IEEE Symposium on VLSI Circuits, 2018
    Co-Authors: Fahim Ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Visvesh S Sathe
    Abstract:

    An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 Processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

Sung Kim - One of the best experts on this subject based on the ideXlab platform.

  • An All-Digital Fused PLL-Buck Architecture for 82% Average V dd -Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • an all digital fused pll buck architecture for 82 average v dd margin reduction in a 0 6 to 1 0 v cortex M0 Processor
    IEEE Journal of Solid-state Circuits, 2019
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microProcessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

  • an all digital unified clock frequency and switched capacitor voltage regulator for variation tolerance in a sub threshold arm cortex M0 Processor
    Symposium on VLSI Circuits, 2018
    Co-Authors: Fahim Ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Visvesh S Sathe
    Abstract:

    An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 Processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

  • VLSI Circuits - An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor
    2018 IEEE Symposium on VLSI Circuits, 2018
    Co-Authors: Fahim Ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Keith Bowman, Visvesh S Sathe
    Abstract:

    An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 Processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

  • ISSCC - A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 Processor
    2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018
    Co-Authors: Xun Sun, Fahim Ur Rahman, Sung Kim, Naveen John, Venkata Rajesh Pamula, Visvesh S Sathe
    Abstract:

    Integrated Voltage Regulation (IVR) using buck converters enables efficient, fine-grained supply-voltage control in modern SoC domains [1]. However, existing IVR implementations face several challenges. As voltage domains continue to shrink, reduced per-domain decoupling capacitance requires rapid IVR transient response, leading to unfavorable efficiency and supply droop margin trade-offs. Additionally, digital domains exhibit a wide load current (I load ) range, requiring capabilities for autonomous transition between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). All-digital IVR solutions are particularly desirable for ease of integration in SoCs.