The Experts below are selected from a list of 5553 Experts worldwide ranked by ideXlab platform
Kunihiro Asada - One of the best experts on this subject based on the ideXlab platform.
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a word parallel digital associative engine with wide search range based on Manhattan Distance
Custom Integrated Circuits Conference, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A word-parallel digital associative engine with accurate and wide-range Manhattan-Distance computation is presented. It performs a continuous search operation to detect not only the nearest-match data but also all data in the sorted order of the exact Manhattan Distance. The word-parallel digital implementation using a hierarchical search path provides a high-speed search operation with faultless precision, a low-voltage operation mode, and a potential capability of unlimited data capacity. Word-parallel Distance calculation circuits autonomously count the Manhattan Distance using a weighted search clock to detect the nearest-match data. An associative engine, with 64 words of 8 bit/spl times/32 element, has been fabricated using a 0.18 /spl mu/m CMOS process and successfully tested. The worst-case search time of all data sorting takes 5.85 /spl mu/s at a supply voltage of 1.8 V.
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a high speed and low voltage associative co processor with exact hamming Manhattan Distance estimation using word parallel and hierarchical search architecture
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan Distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan Distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-/spl mu/m CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.
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A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-Distance estimation using word-parallel and hierarchical search architecture
IEEE Journal of Solid-State Circuits, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan Distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan Distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-/spl mu/m CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.
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CICC - A word-parallel digital associative engine with wide search range based on Manhattan Distance
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 1Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A word-parallel digital associative engine with accurate and wide-range Manhattan-Distance computation is presented. It performs a continuous search operation to detect not only the nearest-match data but also all data in the sorted order of the exact Manhattan Distance. The word-parallel digital implementation using a hierarchical search path provides a high-speed search operation with faultless precision, a low-voltage operation mode, and a potential capability of unlimited data capacity. Word-parallel Distance calculation circuits autonomously count the Manhattan Distance using a weighted search clock to detect the nearest-match data. An associative engine, with 64 words of 8 bit/spl times/32 element, has been fabricated using a 0.18 /spl mu/m CMOS process and successfully tested. The worst-case search time of all data sorting takes 5.85 /spl mu/s at a supply voltage of 1.8 V.
Yusuke Oike - One of the best experts on this subject based on the ideXlab platform.
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a word parallel digital associative engine with wide search range based on Manhattan Distance
Custom Integrated Circuits Conference, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A word-parallel digital associative engine with accurate and wide-range Manhattan-Distance computation is presented. It performs a continuous search operation to detect not only the nearest-match data but also all data in the sorted order of the exact Manhattan Distance. The word-parallel digital implementation using a hierarchical search path provides a high-speed search operation with faultless precision, a low-voltage operation mode, and a potential capability of unlimited data capacity. Word-parallel Distance calculation circuits autonomously count the Manhattan Distance using a weighted search clock to detect the nearest-match data. An associative engine, with 64 words of 8 bit/spl times/32 element, has been fabricated using a 0.18 /spl mu/m CMOS process and successfully tested. The worst-case search time of all data sorting takes 5.85 /spl mu/s at a supply voltage of 1.8 V.
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a high speed and low voltage associative co processor with exact hamming Manhattan Distance estimation using word parallel and hierarchical search architecture
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan Distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan Distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-/spl mu/m CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.
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A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-Distance estimation using word-parallel and hierarchical search architecture
IEEE Journal of Solid-State Circuits, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan Distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan Distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-/spl mu/m CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.
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CICC - A word-parallel digital associative engine with wide search range based on Manhattan Distance
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 1Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A word-parallel digital associative engine with accurate and wide-range Manhattan-Distance computation is presented. It performs a continuous search operation to detect not only the nearest-match data but also all data in the sorted order of the exact Manhattan Distance. The word-parallel digital implementation using a hierarchical search path provides a high-speed search operation with faultless precision, a low-voltage operation mode, and a potential capability of unlimited data capacity. Word-parallel Distance calculation circuits autonomously count the Manhattan Distance using a weighted search clock to detect the nearest-match data. An associative engine, with 64 words of 8 bit/spl times/32 element, has been fabricated using a 0.18 /spl mu/m CMOS process and successfully tested. The worst-case search time of all data sorting takes 5.85 /spl mu/s at a supply voltage of 1.8 V.
Makoto Ikeda - One of the best experts on this subject based on the ideXlab platform.
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a word parallel digital associative engine with wide search range based on Manhattan Distance
Custom Integrated Circuits Conference, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A word-parallel digital associative engine with accurate and wide-range Manhattan-Distance computation is presented. It performs a continuous search operation to detect not only the nearest-match data but also all data in the sorted order of the exact Manhattan Distance. The word-parallel digital implementation using a hierarchical search path provides a high-speed search operation with faultless precision, a low-voltage operation mode, and a potential capability of unlimited data capacity. Word-parallel Distance calculation circuits autonomously count the Manhattan Distance using a weighted search clock to detect the nearest-match data. An associative engine, with 64 words of 8 bit/spl times/32 element, has been fabricated using a 0.18 /spl mu/m CMOS process and successfully tested. The worst-case search time of all data sorting takes 5.85 /spl mu/s at a supply voltage of 1.8 V.
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a high speed and low voltage associative co processor with exact hamming Manhattan Distance estimation using word parallel and hierarchical search architecture
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan Distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan Distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-/spl mu/m CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.
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A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-Distance estimation using word-parallel and hierarchical search architecture
IEEE Journal of Solid-State Circuits, 2004Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan Distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan Distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-/spl mu/m CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.
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CICC - A word-parallel digital associative engine with wide search range based on Manhattan Distance
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 1Co-Authors: Yusuke Oike, Makoto Ikeda, Kunihiro AsadaAbstract:A word-parallel digital associative engine with accurate and wide-range Manhattan-Distance computation is presented. It performs a continuous search operation to detect not only the nearest-match data but also all data in the sorted order of the exact Manhattan Distance. The word-parallel digital implementation using a hierarchical search path provides a high-speed search operation with faultless precision, a low-voltage operation mode, and a potential capability of unlimited data capacity. Word-parallel Distance calculation circuits autonomously count the Manhattan Distance using a weighted search clock to detect the nearest-match data. An associative engine, with 64 words of 8 bit/spl times/32 element, has been fabricated using a 0.18 /spl mu/m CMOS process and successfully tested. The worst-case search time of all data sorting takes 5.85 /spl mu/s at a supply voltage of 1.8 V.
Hans Jurgen Mattausch - One of the best experts on this subject based on the ideXlab platform.
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digital associative memory for word parrallel Manhattan Distance based vector quantization
European Solid-State Circuits Conference, 2012Co-Authors: Seiryu Sasaki, Masahiro Yasuda, Hans Jurgen MattauschAbstract:Digital Word-parallel associative-memory architecture capable of Manhattan-Distance-based vector quantization is reported, which applies frequency dividers and clock counting to realize nearest Manhattan-Distance (MD) search. Experimental verification was done with a 65 nm CMOS design implementing 128 reference vectors, each having 16 components and 16 bit per component. For the fabricated test chips 926 ps minimum search time and 2.13 mW power dissipation are measured at 120MHz and Vdd = 1.2V. At lower supply voltage of Vdd = 0.9V and lower frequency of 20MHz the power-dissipation reduces to 130 μW. In comparison to previous digital architecture a factor 100 smaller power delay product (estimated factor 16 when scaled to 65 nm CMOS) is achieved.
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ESSCIRC - Digital associative memory for word-parrallel Manhattan-Distance-based vector quantization
2012 Proceedings of the ESSCIRC (ESSCIRC), 2012Co-Authors: Seiryu Sasaki, Masahiro Yasuda, Hans Jurgen MattauschAbstract:Digital Word-parallel associative-memory architecture capable of Manhattan-Distance-based vector quantization is reported, which applies frequency dividers and clock counting to realize nearest Manhattan-Distance (MD) search. Experimental verification was done with a 65 nm CMOS design implementing 128 reference vectors, each having 16 components and 16 bit per component. For the fabricated test chips 926 ps minimum search time and 2.13 mW power dissipation are measured at 120MHz and Vdd = 1.2V. At lower supply voltage of Vdd = 0.9V and lower frequency of 20MHz the power-dissipation reduces to 130 μW. In comparison to previous digital architecture a factor 100 smaller power delay product (estimated factor 16 when scaled to 65 nm CMOS) is achieved.
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associative memory with fully parallel nearest Manhattan Distance search for low power real time single chip applications
Asia and South Pacific Design Automation Conference, 2004Co-Authors: Yuji Yano, Tetsushi Koide, Hans Jurgen MattauschAbstract:A fully-parallel minimum Manhattan-Distance search associative memory has been designed in 0.35μm CMOS with 3-metal layers. The nearest-match unit consumes only 1.02mm2, while the chip area is 7.49mm2. The measured winner-search time of this chip, the time to determine the best-matching reference-data word for an input-data word among a database of 128 reference words (5-bit, 16 units), is < 180nsec. This corresponds to a performance requirement of 16 GOPS/mm2, if a 32-bit computer with the same chip area would have to run the same workload. Furthermore the power dissipation of the designed test chip is only about 26.7mW/mm2.
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ASP-DAC - Associative memory with fully parallel nearest-Manhattan-Distance search for low-power real-time single-chip applications
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 1Co-Authors: Yuji Yano, Tetsushi Koide, Hans Jurgen MattauschAbstract:A fully-parallel minimum Manhattan-Distance search associative memory has been designed in 0.35μm CMOS with 3-metal layers. The nearest-match unit consumes only 1.02mm2, while the chip area is 7.49mm2. The measured winner-search time of this chip, the time to determine the best-matching reference-data word for an input-data word among a database of 128 reference words (5-bit, 16 units), is < 180nsec. This corresponds to a performance requirement of 16 GOPS/mm2, if a 32-bit computer with the same chip area would have to run the same workload. Furthermore the power dissipation of the designed test chip is only about 26.7mW/mm2.
Bonifacio Martindelbrio - One of the best experts on this subject based on the ideXlab platform.
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topology preservation in sofm an euclidean versus Manhattan Distance comparison
International Work-Conference on Artificial and Natural Neural Networks, 1999Co-Authors: Nicolas J Medranomarques, Bonifacio MartindelbrioAbstract:The Self-Organising Feature Map (SOFM) is one of the unsupervised neural models of most widespread use. Several studies have been carried out in order to determine the degree of topology-preservation for this data projection method, and the influence of the Distance measure used, usually Euclidean or Manhattan Distance. In this paper, by using a new topology-preserving representation of the SOFM and the well-known Sammon’s stress, graphical and numerical comparisons are shown between both possibilities for the Distance measure. Our projection method, based on the relative Distances between neighbouring neurons, gives similar information to those of the Sammon projection, but in a graphical way.