The Experts below are selected from a list of 312 Experts worldwide ranked by ideXlab platform

Elias Fries - One of the best experts on this subject based on the ideXlab platform.

Yen-chin Liao - One of the best experts on this subject based on the ideXlab platform.

  • Static floating-point unit with implicit exponent tracking for embedded DSP
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: Chie-min Chao, Yen-chin Liao
    Abstract:

    Embedded DSP applications demand more dynamic range and higher precision to prevent overflow and improve the quality respectively. The most straightforward way to satisfy both is to use the floating-point arithmetic, where the data samples are represented in the exponent and the Mantissa parts and the data are normalized for every operation. Designers prefer fixed-point arithmetic with much simpler hardware, but they need to frequently and explicitly scale down the intermediate results to prevent overflow. In this paper, we propose an alternative-static floating-point unit where the operands are represented in the normalized fractional numbers, similar to the Mantissa part in the floating-point units. We use static techniques instead to normalize the intermediate values with implicit exponent tracking in our software tool. The simulation result shows that the proposed approach improves both the rounding error and the execution cycles of the fixed-point units with similar hardware complexity.

  • ISCAS (2) - Static floating-point unit with implicit exponent tracking for embedded DSP
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: Chie-min Chao, Yen-chin Liao
    Abstract:

    Embedded DSP applications demand more dynamic range and higher precision to prevent overflow and improve the quality respectively. The most straightforward way to satisfy both is to use the floating-point arithmetic, where the data samples are represented in the exponent and the Mantissa parts and the data are normalized for every operation. Designers prefer fixed-point arithmetic with much simpler hardware, but they need to frequently and explicitly scale down the intermediate results to prevent overflow. In this paper, we propose an alternative-static floating-point unit where the operands are represented in the normalized fractional numbers, similar to the Mantissa part in the floating-point units. We use static techniques instead to normalize the intermediate values with implicit exponent tracking in our software tool. The simulation result shows that the proposed approach improves both the rounding error and the execution cycles of the fixed-point units with similar hardware complexity.

Chie-min Chao - One of the best experts on this subject based on the ideXlab platform.

  • Static floating-point unit with implicit exponent tracking for embedded DSP
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: Chie-min Chao, Yen-chin Liao
    Abstract:

    Embedded DSP applications demand more dynamic range and higher precision to prevent overflow and improve the quality respectively. The most straightforward way to satisfy both is to use the floating-point arithmetic, where the data samples are represented in the exponent and the Mantissa parts and the data are normalized for every operation. Designers prefer fixed-point arithmetic with much simpler hardware, but they need to frequently and explicitly scale down the intermediate results to prevent overflow. In this paper, we propose an alternative-static floating-point unit where the operands are represented in the normalized fractional numbers, similar to the Mantissa part in the floating-point units. We use static techniques instead to normalize the intermediate values with implicit exponent tracking in our software tool. The simulation result shows that the proposed approach improves both the rounding error and the execution cycles of the fixed-point units with similar hardware complexity.

  • ISCAS (2) - Static floating-point unit with implicit exponent tracking for embedded DSP
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: Chie-min Chao, Yen-chin Liao
    Abstract:

    Embedded DSP applications demand more dynamic range and higher precision to prevent overflow and improve the quality respectively. The most straightforward way to satisfy both is to use the floating-point arithmetic, where the data samples are represented in the exponent and the Mantissa parts and the data are normalized for every operation. Designers prefer fixed-point arithmetic with much simpler hardware, but they need to frequently and explicitly scale down the intermediate results to prevent overflow. In this paper, we propose an alternative-static floating-point unit where the operands are represented in the normalized fractional numbers, similar to the Mantissa part in the floating-point units. We use static techniques instead to normalize the intermediate values with implicit exponent tracking in our software tool. The simulation result shows that the proposed approach improves both the rounding error and the execution cycles of the fixed-point units with similar hardware complexity.

Paolo Ienne - One of the best experts on this subject based on the ideXlab platform.

  • FPGA - Reducing the cost of floating-point Mantissa alignment and normalization in FPGAs
    Proceedings of the ACM SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12, 2012
    Co-Authors: Yehdhih Ould Mohammed Moctar, Paolo Ienne, Nithin George, Guy G F Lemieux, Hadi Parandeh-afshar, Philip Brisk
    Abstract:

    In floating-point datapaths synthesized on FPGAs, the shifters that perform Mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers; unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network; these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point Mantissa alignment and normalization; the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

  • reducing the cost of floating point Mantissa alignment and normalization in fpgas
    Field Programmable Gate Arrays, 2012
    Co-Authors: Yehdhih Ould Mohammed Moctar, Paolo Ienne, Nithin George, Hadi Parandehafshar, Guy G F Lemieux, Philip Brisk
    Abstract:

    In floating-point datapaths synthesized on FPGAs, the shifters that perform Mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers; unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network; these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point Mantissa alignment and normalization; the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

  • fpga implementation of a single precision floating point multiply accumulator with single cycle accumulation
    Field-Programmable Custom Computing Machines, 2009
    Co-Authors: Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne
    Abstract:

    This paper describes an FPGA implementation of a single-precision floating-point multiply-accumulator (FPMAC) that supports single-cycle accumulation while maintaining high clock frequencies. A non-traditional internal representation reduces the cost of Mantissa alignment within the accumulator. The FPMAC is evaluated on an Altera Stratix III FPGA.

L Shao - One of the best experts on this subject based on the ideXlab platform.

  • empirical Mantissa distributions of pulsars
    Astroparticle Physics, 2010
    Co-Authors: L Shao
    Abstract:

    Abstract The occurrence of digits one through nine as the leftmost nonzero digit of numbers from real world sources is often not uniformly distributed, but instead, is distributed according to a logarithmic law, known as Benford’s law. Here, we investigate systematically the Mantissa distributions of some pulsar quantities, and find that for most quantities their first digits conform to this law. However, the barycentric period shows significant deviation from the usual distribution, but satisfies a generalized Benford’s law roughly. Therefore pulsars can serve as an ideal assemblage to study the first digit distributions of real world data, and the observations can be used to constrain theoretical models of pulsar behavior.