The Experts below are selected from a list of 56199 Experts worldwide ranked by ideXlab platform

A Ripp - One of the best experts on this subject based on the ideXlab platform.

  • dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.

  • date 2006 special session dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices

Markus Buhler - One of the best experts on this subject based on the ideXlab platform.

  • dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.

  • date 2006 special session dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices

Conny Östman - One of the best experts on this subject based on the ideXlab platform.

  • benzothiazole benzotriazole and their derivates in clothing textiles a potential source of environmental pollutants and human exposure
    Environmental Science and Pollution Research, 2015
    Co-Authors: Rozanna Avagyan, Giovanna Luongo, Gunnar Thorsén, Conny Östman
    Abstract:

    Textiles play an important role in our daily life, and textile production is one of the oldest industries. In the Manufacturing Chain from natural and/or synthetic fibers to the final clothing products, the use of many different chemicals is ubiquitous. A lot of research has focused on chemicals in textile wastewater, but the knowledge of the actual content of harmful chemicals in clothes sold on the retail market is limited. In this paper, we have focused on eight benzothiazole and benzotriazole derivatives, compounds rated as high production volume chemicals. Twenty-six clothing samples of various textile materials and colors manufactured in 14 different countries were analyzed in textile clothing using liquid chromatography tandem mass spectrometry. Among the investigated textile products, 11 clothes were for babies, toddlers, and children. Eight of the 11 compounds included in the investigation were detected in the textiles. Benzothiazole was present in 23 of 26 investigated garments in concentrations ranging from 0.45 to 51 μg/g textile. The garment with the highest concentration of benzothiazole contained a total amount of 8.3 mg of the chemical. The third highest concentration of benzothiazole (22 μg/g) was detected in a baby body made from "organic cotton" equipped with the "Nordic Ecolabel" ("Svanenmarkt"). It was also found that concentrations of benzothiazoles in general were much higher than those for benzotriazoles. This study implicates that clothing textiles can be a possible route for human exposure to harmful chemicals by skin contact, as well as being a potential source of environmental pollutants via laundering and release to household wastewater.

  • benzothiazole benzotriazole and their derivates in clothing textiles a potential source of environmental pollutants and human exposure
    Environmental Science and Pollution Research, 2015
    Co-Authors: Rozanna Avagyan, Giovanna Luongo, Gunnar Thorsén, Conny Östman
    Abstract:

    Textiles play an important role in our daily life, and textile production is one of the oldest industries. In the Manufacturing Chain from natural and/or synthetic fibers to the final clothing prod ...

Ulf Schlichtmann - One of the best experts on this subject based on the ideXlab platform.

  • dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.

  • date 2006 special session dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices

R. Sommer - One of the best experts on this subject based on the ideXlab platform.

  • dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.

  • date 2006 special session dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed signal circuit design
    Design Automation and Test in Europe, 2006
    Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A Ripp
    Abstract:

    The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit design, physical design and Manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and Manufacturing Chain lead to high costs of multiple Manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices