The Experts below are selected from a list of 1947 Experts worldwide ranked by ideXlab platform
Chris Toumazou - One of the best experts on this subject based on the ideXlab platform.
-
Towards high Frequency switched-current filters in CMOS and GaAs technology
1993 IEEE International Symposium on Circuits and Systems (ISCAS), 1993Co-Authors: N.c. Battersby, Chris ToumazouAbstract:The switched-current technique is a relatively new analog sampled-data signal processing technique which aims at replacing switched capacitors by offering superior digital process compatibility and the potential for higher operating frequencies. The high Frequency potential of switched-currents is explored by showing an integrated fifth-order bilinear elliptic filter, operating at a Maximum Clock Frequency of 5.75 MHz, and the first implementation of switched currents in GaAs MESFET technology, with a simulated Clock Frequency of 1 GHz.
-
ISCAS - Towards high Frequency switched-current filters in CMOS and GaAs technology
1993 IEEE International Symposium on Circuits and Systems, 1993Co-Authors: N.c. Battersby, Chris ToumazouAbstract:The switched-current technique is a relatively new analog sampled-data signal processing technique which aims at replacing switched capacitors by offering superior digital process compatibility and the potential for higher operating frequencies. The high Frequency potential of switched-currents is explored by showing an integrated fifth-order bilinear elliptic filter, operating at a Maximum Clock Frequency of 5.75 MHz, and the first implementation of switched currents in GaAs MESFET technology, with a simulated Clock Frequency of 1 GHz. >
Mrityunjoy Chakraborty - One of the best experts on this subject based on the ideXlab platform.
-
NCC - FPGA based implementation of high speed tunable notch filter using pipelining and unfolding
2014 Twentieth National Conference on Communications (NCC), 2014Co-Authors: Sounak Samanta, Mrityunjoy ChakrabortyAbstract:In this paper, we present a Field-Programmable-Gate-Array (FPGA) based design and implementation of extremely high speed realization of tunable Infinite Impulse Response (IIR) notch filter. The basic 2nd ordered tunable notch filter structure is implementable in Xilinx Virtex-5 FPGA with Maximum Clock Frequency of ∼80MHz. Here, we propose a FPGA based design of extremely high speed tunable notch filter effectively operating at Maximum Clock Frequency of ∼1200MHz with the help of Scattered-Look-Ahead (SLA) pipelining with power-of-2-decomposition approach, proper retiming and unfolding applied over its basic low-speed structure. To generalize its FPGA based design for specific speed up factor, a new efficient simpler approach utilizing Pascal's Triangle is proposed to calculate the multiplier coefficients of feed-forward and feedback sections of extremely high speed notch filter. The post place & route synthesis results for its FPGA design are obtained by generating VHDL code showing that proposed restructured notch filter can operate effectively greater than 1200MHz Clock Frequency meeting the present days' certain industry's needs.
-
FPGA based implementation of high speed tunable notch filter using pipelining and unfolding
2014 Twentieth National Conference on Communications (NCC), 2014Co-Authors: Sounak Samanta, Mrityunjoy ChakrabortyAbstract:In this paper, we present a Field-Programmable-Gate-Array (FPGA) based design and implementation of extremely high speed realization of tunable Infinite Impulse Response (IIR) notch filter. The basic 2nd ordered tunable notch filter structure is implementable in Xilinx Virtex-5 FPGA with Maximum Clock Frequency of ~80MHz. Here, we propose a FPGA based design of extremely high speed tunable notch filter effectively operating at Maximum Clock Frequency of ~1200MHz with the help of Scattered-Look-Ahead (SLA) pipelining with power-of-2-decomposition approach, proper retiming and unfolding applied over its basic low-speed structure. To generalize its FPGA based design for specific speed up factor, a new efficient simpler approach utilizing Pascal's Triangle is proposed to calculate the multiplier coefficients of feed-forward and feedback sections of extremely high speed notch filter. The post place & route synthesis results for its FPGA design are obtained by generating VHDL code showing that proposed restructured notch filter can operate effectively greater than 1200MHz Clock Frequency meeting the present days' certain industry's needs.
J.d. Meindl - One of the best experts on this subject based on the ideXlab platform.
-
impact of die to die and within die parameter fluctuations on the Maximum Clock Frequency distribution for gigascale integration
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Keith Bowman, S.g. Duvall, J.d. MeindlAbstract:A model describing the Maximum Clock Frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations.
-
Impact of within-die parameter fluctuations on future Maximum Clock Frequency distributions
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169), 2001Co-Authors: K.a. Bowman, J.d. MeindlAbstract:The impact of parameter fluctuations on future circuit performance is evaluated by employing rigorously derived device and circuit models to calculate the critical path delay distributions resulting from die-to-die and within-die fluctuations. Utilizing these distributions with a recently derived FMAX distribution model validated by measured data, the effect of within-die fluctuations on the FMAX mean is forecast for the 180, 130, 100, 70 and 50 nm technology generations. Systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50 nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. This analysis should encourage efforts toward tightening within-die process controls and developing circuit design methodologies that suppress the impact of within-die parameter fluctuations on circuit performance.
-
Impact of die-to-die and within-die parameter fluctuations on the Maximum Clock Frequency distribution
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001Co-Authors: K.a. Bowman, S.g. Duvall, J.d. MeindlAbstract:A processor Maximum Clock Frequency (FMAX) distribution is significantly influenced by the magnitude of critical path delay deviations resulting from both die-to-die (inter-die) and within-die (intra-die) fluctuations. FMAX is a measurement performed at wafer sort in which each functional die is tested for its Maximum operating Clock Frequency. Die-to-die fluctuations resulting from lot-to-lot, wafer-to-wafer and some sources of the within-wafer variations affect every element on a chip equally. Conversely, within-die fluctuations consisting of both random and systematic components produce a nonuniformity of electrical characteristics across the chip. The FMAX distribution model is based upon statistical simulations of critical paths for a 0.25/spl mu/m Pentium-family processor.
N.c. Battersby - One of the best experts on this subject based on the ideXlab platform.
-
Towards high Frequency switched-current filters in CMOS and GaAs technology
1993 IEEE International Symposium on Circuits and Systems (ISCAS), 1993Co-Authors: N.c. Battersby, Chris ToumazouAbstract:The switched-current technique is a relatively new analog sampled-data signal processing technique which aims at replacing switched capacitors by offering superior digital process compatibility and the potential for higher operating frequencies. The high Frequency potential of switched-currents is explored by showing an integrated fifth-order bilinear elliptic filter, operating at a Maximum Clock Frequency of 5.75 MHz, and the first implementation of switched currents in GaAs MESFET technology, with a simulated Clock Frequency of 1 GHz.
-
ISCAS - Towards high Frequency switched-current filters in CMOS and GaAs technology
1993 IEEE International Symposium on Circuits and Systems, 1993Co-Authors: N.c. Battersby, Chris ToumazouAbstract:The switched-current technique is a relatively new analog sampled-data signal processing technique which aims at replacing switched capacitors by offering superior digital process compatibility and the potential for higher operating frequencies. The high Frequency potential of switched-currents is explored by showing an integrated fifth-order bilinear elliptic filter, operating at a Maximum Clock Frequency of 5.75 MHz, and the first implementation of switched currents in GaAs MESFET technology, with a simulated Clock Frequency of 1 GHz. >
Antonio G.m. Strollo - One of the best experts on this subject based on the ideXlab platform.
-
A high performance floating-point special function unit using constrained piecewise quadratic approximation
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: Davide De Caro, Nicola Petra, Antonio G.m. StrolloAbstract:A special function unit, able to compute square root, reciprocal square root, logarithm and exponential functions is presented in this paper. The system supports single precision IEEE-754 floating-point standard and uses a novel constrained piecewise quadratic interpolation technique to approximate the implemented functions. The proposed approach allows to reduce look-up table size of 40% with respect to previously proposed techniques. The SFU has been implemented in a test chip in 0.18 mum CMOS. A Maximum Clock Frequency of 420 MHz and a power dissipation of 160 mW@420 MHz have been measured.
-
ISCAS - A high performance floating-point special function unit using constrained piecewise quadratic approximation
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: Davide De Caro, Nicola Petra, Antonio G.m. StrolloAbstract:A special function unit, able to compute square root, reciprocal square root, logarithm and exponential functions is presented in this paper. The system supports single precision IEEE-754 floating-point standard and uses a novel constrained piecewise quadratic interpolation technique to approximate the implemented functions. The proposed approach allows to reduce look-up table size of 40% with respect to previously proposed techniques. The SFU has been implemented in a test chip in 0.18 mum CMOS. A Maximum Clock Frequency of 420 MHz and a power dissipation of 160 mW@420 MHz have been measured.