The Experts below are selected from a list of 483585 Experts worldwide ranked by ideXlab platform

Panfilo C Deguzman - One of the best experts on this subject based on the ideXlab platform.

Gregory P Nordin - One of the best experts on this subject based on the ideXlab platform.

Vadim Issakov - One of the best experts on this subject based on the ideXlab platform.

  • transformer coupled octa core 60 ghz push push vco in a 45 nm rf soi cmos technology
    2019 IEEE International Conference on Microwaves Antennas Communications and Electronic Systems (COMCAS), 2019
    Co-Authors: J Rimmelspacher, Robert Weigel, Vadim Issakov
    Abstract:

    This work presents a 60 GHz octa-core push-push VCO in a 45 nm partially depleted (PD) Silicon-on-Insulator (SOI) CMOS technology. We investigate the feasibility of coupling eight VCO cores via resonant-tank transformers and discuss circuit topology considerations. The Measured Phase noise at 63.4 GHz is -95.3dB/Hz at 1 MHz offset from carrier. The continuous frequency-tuning range is 19 %. The eight VCO cores consume in total 80 mW DC power. The complete circuit, including buffers at the fundamental and second harmonic outputs, draws 158 mA from a single 1 V supply. The total area of the octa-core VCO excluding pads is 0.18 mm2.

  • lc tank differential inductor coupled dual core 60 ghz push push vco in 45 nm rf soi cmos technology
    Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2019
    Co-Authors: J Rimmelspacher, Robert Weigel, Amelie Hagelauer, Vadim Issakov
    Abstract:

    This paper presents a 60 GHz dual-core push-push VCO in a 45 nm partially depleted (PD) RF Silicon-on-Insulator (SOI) CMOS technology. The cores are coupled inductively via differential inductors. The best Measured Phase noise at 1 MHz offset from a 63 GHz carrier is -$94.4 dBc/Hz. The wideband continuous frequency-tuning-range (FTR) is 16 %. The DC power dissipation is 76 mW including fundamental 30 GHz and second harmonic (H2) 60 GHz output buffers at 1 V power supply voltage. The measurement results of a reference single-core VCO design proves the relative Phase noise improvement of the implemented core-coupling technique. The chip area excluding pads is 0.09 mm2.

Kevin J Chen - One of the best experts on this subject based on the ideXlab platform.

  • a low jitter low Phase noise 10 ghz sub harmonically injection locked pll with self aligned dll in 65 nm cmos technology
    IEEE Transactions on Microwave Theory and Techniques, 2014
    Co-Authors: Hongyeh Chang, Menghan Li, Kevin J Chen
    Abstract:

    In this paper, we present design and analysis of an innovative low-jitter low-Phase-noise 10-GHz sub-harmonically injection-locked Phase-locked loop (PLL) with self-aligned delay-locked loop in 65-nm CMOS technology. With the proposed innovative topology, the Phase between the injection signal and the voltage-controlled oscillator in the PLL can be dynamically aligned to minimize the jitter over the variations. A modified theoretical model of the sub-harmonically injection-locked PLL with self-aligned injection is developed for the design methodology. The in-band Phase noise of the sub-harmonically injection-locked PLL can be significantly improved using the self-aligned sub-harmonically injection-locked technique. The design considerations of the locking range, loop bandwidth, and frequency division ratio are addressed. At 10 GHz, the Measured Phase noise of the proposed PLL with self-aligned injection at 1-MHz offset is -130.2 dBc/Hz with a root-mean-square jitter of 44 fs. The total dc power consumption is 62.7 mW. From 10 °C to 70 °C, the Measured Phase noise at 1-MHz offset and jitter are better than -129 dBc/Hz and 48 fs, respectively. This work demonstrates excellent performance and good robustness over the variations, and it can be compared to the previously reported state-of-the-art sub-harmonically injection-locked PLLs.

Lute Maleki - One of the best experts on this subject based on the ideXlab platform.