The Experts below are selected from a list of 72 Experts worldwide ranked by ideXlab platform
Glenn R Wylie - One of the best experts on this subject based on the ideXlab platform.
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forgetting as an active process an fmri investigation of item method directed forgetting
Cerebral Cortex, 2008Co-Authors: Glenn R Wylie, John J Foxe, Tracy L TaylorAbstract:Using event-related functional magnetic resonance imaging (fMRI), we examined the blood oxygen level--dependent response associated with intentional remembering and forgetting. In an itemmethod directed forgetting paradigm, participants were presented with words, one at a time, each of which was followed after a brief delay by an Instruction to Remember or Forget. Behavioral data revealed a directed forgetting effect: greater recognition of to-beremembered than to-be-forgotten words. We used this behavioral recognition data to sort the fMRI data into 4 conditions based on the combination of Memory Instruction and behavioral outcome. When contrasted with unintentional forgetting, intentional forgetting was associated with increased activity in hippocampus (Broadmann area [BA] 35) and superior frontal gyrus (BA10/11); when contrasted with intentional remembering, intentional forgetting was associated with activity in medial frontal gyrus (BA10), middle temporal gyrus (BA21), parahippocampal gyrus (BA34 and 35), and cingulate gyrus (BA31). Thus, intentional forgetting depends on neural structures distinctfromthoseinvolvedinunintentionalforgettingandintentional remembering. These results challenge the standard selective rehearsal account of item-method directed forgetting and suggest that frontal control processes may be critical for directed forgetting.
Michael L. Scott - One of the best experts on this subject based on the ideXlab platform.
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Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors
University of Rochester. Computer Science Department., 2014Co-Authors: John M. Mellor-crummey, Michael L. ScottAbstract:Busy-wait techniques are heavily used for mutual exclusion and barrier synchronization in shared-Memory parallel programs. Unfortunately, typical implementations of busy-waiting tend to produce large amounts of Memory and interconnect contention, introducing performance bottlenecks that become markedly more pronounced as applications scale. We argue that this problem is not fundamental, and that one can in fact construct busy-wait synchronization algorithms that induce no Memory or interconnect contention. The key to these algorithms is for every processor to spin on separate locally-accessible flag variables, and for some other processor to terminate the spin with a single remote write operation at an appropriate time. Flag variables may be locally-accessible as a result of coherent caching, or by virtue of allocation in the local portion of physically distributed shared Memory. We present a new scalable algorithm for spin locks that generates O(1) remote references per lock acquisition, independent of the number of processors attempting to acquire the lock. Our algorithm provides reasonable latency in the absence of contention, requires only a constant amount of space per lock, and requires no hardware support other than a swap-with-Memory Instruction. We also present a new scalable barrier algorithm that generates O(1) remote references per processor reaching the barrier, and observe that two previously-known barriers can likewise be cast in a form that spins only on locally-accessible flag variables. None of these barrier algorithms requires hardware support beyond the usual atomicity of Memory reads and writes. We compare the performance of our scalable algorithms with other software approaches to busy-wait synchronization on both a Sequent Symmetry and a BBN Butterfly. Our principal conclusion is that contention due to synchronization need not be a problem in large-scale shared-Memory multiprocessors. The existence of scalable algorithms greatly weakens the case for costly special-purpose hardware support for synchronization, and provides a case against so-called ``dance hall'' architectures, in which shared Memory locations are equally far from all processors. The postscript here is the version from which the galleys were prepared
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Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors
University of Rochester. Computer Science Department., 2012Co-Authors: John M. Mellor-crummey, Michael L. ScottAbstract:Busy-wait techniques are heavily used for mutual exclusion and barrier synchronization in shared-Memory parallel programs. Unfortunately, typical implementations of busy-waiting tend to produce large amounts of Memory and interconnect contention, introducing performance bottlenecks that become markedly more pronounced as applications scale. We argue in this paper that this problem is not fundamental, and that one can in fact construct busy-wait synchronization algorithms that induce no Memory or interconnect contention. The key to these algorithms is for every processor to spin on a separate location in local Memory, and for some other processor to terminate the spin with a single remote write operation at an appropriate time. Locations on which to spin may be local as a result of coherent caching, or by virtue of static allocation in the local portion of physically distributed shared Memory. We present a new scalable algorithm for spin locks that generates O(1) remote references per lock acquisition, independent of the number of processors attempting to acquire the lock. Our algorithm provides reasonable latency in the absence of contention, requires only a constant amount of space per lock, and requires no hardware support other than a swap-with-Memory Instruction. We also present a new scalable barrier algorithm that generates O(1) remote references per processor reaching the barrier, and observe that two previously-known barriers can likewise be cast in a form that spins only on local locations. None of these barrier algorithms requires hardware support beyond the usual atomicity of Memory reads and writes. We compare the performance of our scalable algorithms with other software approaches to busy-wait synchronization on both a Sequent Symmetry and a BBN Butterfly. Our principal conclusion is that contention due to synchronization need not be a problem in large-scale shared-Memory multiprocessors. The existence of scalable algorithms greatly weakens the case for costly special-purpose hardware support for synchronization, and provides a case against so-called "dance hall" architectures, in which shared Memory locations are equally far from all processors
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2008Co-Authors: John M. Mellor-crummey, Michael L. ScottAbstract:Busy-wait techniques are heavily used for mutual exclusion and barrier synchronization in shared-Memory parallel programs Unfortunately, typical implementations of busy-waiting tend to produce large amounts of Memory and interconnect contention, introducing performance bottlenecks that become markedly more pronounced as applications scale. We argue that this problem is not fundamental, and that one can in fact construct busy-wait synchronization algorithms that induce no Memory or interconnect contention. The key to these algorithms is for every processor to spin on separate locally-accessible flag variables, and for some other processor to terminate the spin with a single remote write operation at an appropriate time. Flag variables may be locally-accessible as a result of coherent caching, or by virtue of allocation in the local portion of physically distributed shared Memory We present a new scalable algorithm for spin locks that generates O(1) remote references per lock acquisition, independent of the number of processors attempting to acquire the lock. Our algorithm provides reasonable latency in the absence of contention, requires only a constant amount of space per lock, and requires no hardware support other than a swap-with-Memory Instruction. We also present a new scalable barrier algorithm that generates O(1) remot
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algorithms for scalable synchronization on shared Memory multiprocessors
ACM Transactions on Computer Systems, 1991Co-Authors: John Mellorcrummey, Michael L. ScottAbstract:Busy-wait techniques are heavily used for mutual exclusion and barrier synchronization in shared-Memory parallel programs. Unfortunately, typical implementations of busy-waiting tend to produce large amounts of Memory and interconnect contention, introducing performance bottlenecks that become markedly more pronounced as applications scale. We argue that this problem is not fundamental, and that one can in fact construct busy-wait synchronization algorithms that induce no Memory or interconnect contention. The key to these algorithms is for every processor to spin on separate locally-accessible flag variables, and for some other processor to terminate the spin with a single remote write operation at an appropriate time. Flag variables may be locally-accessible as a result of coherent caching, or by virtue of allocation in the local portion of physically distributed shared Memory. We present a new scalable algorithm for spin locks that generates 0(1) remote references per lock acquisition, independent of the number of processors attempting to acquire the lock. Our algorithm provides reasonable latency in the absence of contention, requires only a constant amount of space per lock, and requires no hardware support other than a swap-with-Memory Instruction. We also present a new scalable barrier algorithm that generates 0(1) remote references per processor reaching the barrier, and observe that two previously-known barriers can likewise be cast in a form that spins only on locally-accessible flag variables. None of these barrier algorithms requires hardware support beyond the usual atomicity of Memory reads and writes. We compare the performance of our scalable algorithms with other software approaches to busy-wait synchronization on both a Sequent Symmetry and a BBN Butterfly. Our principal conclusion is that contention due to synchronization need not be a problem in large-scale shared-Memory multiprocessors. The existence of scalable algorithms greatly weakens the case for costly special-purpose hardware support for synchronization, and provides a case against so-called “dance hall” architectures, in which shared Memory locations are equally far from all processors. —From the Authors' Abstract
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Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors
1991Co-Authors: John M. Mellor-crummey, Michael L. ScottAbstract:Busy-wait techniques are heavily used for mutual exclusion and barrier synchronization in shared-Memory parallel programs Unfortunately, typical implementations of busy-waiting tend to produce large amounts of Memory and interconnect contention, introducing performance bottlenecks that become markedly more pronounced as apphcations scale. We argue that this problem is not fundamental, and that one can in fact construct busy wait synchronization algorithms that induce no Memory or interconnect contention, The key to these algorithms is for every processor to spin on separate locally-accessible flag variables, and for some other processor to terminate the spin with a single remote write operation at an appropriate time. Flag variables may lbe locally-accessible as a result of coherent caching, or by virtue of allocation m the local portion of physically distributed shared Memory We present a new scalable algorithm for spin locks that generates 0(1) remote references per lock acquisition, independent of the number of processors attempting to acquire the lock Our algorithm provides reasonable latency in the absence of contention, requires only a constant amount of space per lock, and requires no hardware support other than a swap-with-Memory Instruction. We also present a new scalable barrier algorithm that generates O(1) remot
Johanna Kissler - One of the best experts on this subject based on the ideXlab platform.
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forget me not remembering forget items versus un cued items in directed forgetting
Frontiers in Psychology, 2015Co-Authors: Bastian Zwissler, Helena Fischer, Sebastian Schindler, Christian Plewnia, Johanna KisslerAbstract:Humans need to be able to selectively control their memories. This capability is often investigated in directed forgetting (DF) paradigms. In item-method DF, individual items are presented and each is followed by either a forget- or remember-Instruction. On a surprise test of all items, Memory is then worse for to-be-forgotten items (TBF) compared to to-be-remembered items (TBR). This is thought to result mainly from selective rehearsal of TBR, although inhibitory mechanisms also appear to be recruited by this paradigm. Here, we investigate whether the mnemonic consequences of a forget Instruction differ from the ones of incidental encoding, where items are presented without a specific Memory Instruction. Four experiments were conducted where un-cued items (UI) were interspersed and recognition performance was compared between TBR, TBF, and UI stimuli. Accuracy was encouraged via a performance-dependent monetary bonus. Experiments varied the number of items and their presentation speed and used either letter-cues or symbolic cues. Across all experiments, including perceptually fully counterbalanced variants, Memory accuracy for TBF was reduced compared to TBR, but better than for UI. Moreover, participants made consistently fewer false alarms and used a very conservative response criterion when responding to TBF stimuli. Thus, the F-cue results in active processing and reduces false alarm rate, but this does not impair recognition Memory beyond an un-cued baseline condition, where only incidental encoding occurs. Theoretical implications of these findings are discussed.
Tracy L Taylor - One of the best experts on this subject based on the ideXlab platform.
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forgetting as an active process an fmri investigation of item method directed forgetting
Cerebral Cortex, 2008Co-Authors: Glenn R Wylie, John J Foxe, Tracy L TaylorAbstract:Using event-related functional magnetic resonance imaging (fMRI), we examined the blood oxygen level--dependent response associated with intentional remembering and forgetting. In an itemmethod directed forgetting paradigm, participants were presented with words, one at a time, each of which was followed after a brief delay by an Instruction to Remember or Forget. Behavioral data revealed a directed forgetting effect: greater recognition of to-beremembered than to-be-forgotten words. We used this behavioral recognition data to sort the fMRI data into 4 conditions based on the combination of Memory Instruction and behavioral outcome. When contrasted with unintentional forgetting, intentional forgetting was associated with increased activity in hippocampus (Broadmann area [BA] 35) and superior frontal gyrus (BA10/11); when contrasted with intentional remembering, intentional forgetting was associated with activity in medial frontal gyrus (BA10), middle temporal gyrus (BA21), parahippocampal gyrus (BA34 and 35), and cingulate gyrus (BA31). Thus, intentional forgetting depends on neural structures distinctfromthoseinvolvedinunintentionalforgettingandintentional remembering. These results challenge the standard selective rehearsal account of item-method directed forgetting and suggest that frontal control processes may be critical for directed forgetting.
Mark Guzdial - One of the best experts on this subject based on the ideXlab platform.
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measuring cognitive load in introductory cs adaptation of an instrument
International Computing Education Research Workshop, 2014Co-Authors: Briana B. Morrison, Brian Dorn, Mark GuzdialAbstract:A student's capacity to learn a concept is directly related to how much cognitive load is used to comprehend the material. The central problem identified by Cognitive Load Theory is that learning is impaired when the total amount of processing requirements exceeds the limited capacity of working Memory. Instruction can impose three different types of cognitive load on a student's working Memory: intrinsic load, extraneous load, and germane load. Since working Memory is a fixed size, Instructional material should be designed to minimize the extraneous and intrinsic loads in order to increase the amount of Memory available for the germane load. This will improve learning. To effectively design Instruction to minimize cognitive load we must be able to measure the specific load components for any pedagogical intervention. This paper reports on a study that adapts a previously developed instrument to measure cognitive load. We report on the adaptation of the instrument to a new discipline, introductory computer science, and the results of measuring the cognitive load factors of specific lectures. We discuss the implications for the ability to measure specific cognitive load components and use of the tool in future studies.