The Experts below are selected from a list of 46101 Experts worldwide ranked by ideXlab platform

Kambiz Kaviani - One of the best experts on this subject based on the ideXlab platform.

  • ISSCC - A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
    IEEE Journal of Solid-State Circuits, 2014
    Co-Authors: Michael Bucher, Ravi Kollipara, Liji Gopalakrishnan, Pravin Kumar Venkatesan, Barry Daly, Kambiz Kaviani, Kashinath Prabhu, B. William F. Stonecypher, Wayne Dettloff
    Abstract:

    The emergence of cloud computing has driven the demand for high-density, low-latency and high-speed Memory Interfaces. For such applications the use of multiple dual-inline Memory modules (DIMMs) with multiple ranks enables time-efficient processing of high-volume data. However, the deterioration of the channel frequency response due to the presence of DIMM connectors and multiple ranks makes it challenging to perform low-power read and write (R/W) operations at high-speed. Recent works have demonstrated the use of near-ground signaling (NGS) for low-power operation and signal-integrity enhancement with the aid of transmit supply regulation. In contrast to their differential nature, this paper introduces a single-ended NGS transceiver that achieves 6.4Gb/s R/W operations with the aid of low-power equalization and in-situ reference-voltage calibration over a 3.5" total FR4 PCB routing with more than 25mm of package traces in a dual-rank DIMM Memory Interface system.

  • a 6 4 gb s near ground single ended transceiver for dual rank dimm Memory Interface systems
    International Solid-State Circuits Conference, 2013
    Co-Authors: Michael Bucher, Ravi Kollipara, Liji Gopalakrishnan, Pravin Kumar Venkatesan, Barry Daly, Kambiz Kaviani, Kashinath Prabhu, William B F Stonecypher, Wayne Dettloff, Teva Stone
    Abstract:

    The emergence of cloud computing has driven the demand for high-density, low-latency and high-speed Memory Interfaces. For such applications the use of multiple dual-inline Memory modules (DIMMs) with multiple ranks enables time-efficient processing of high-volume data. However, the deterioration of the channel frequency response due to the presence of DIMM connectors and multiple ranks makes it challenging to perform low-power read and write (R/W) operations at high-speed. Recent works have demonstrated the use of near-ground signaling (NGS) for low-power operation and signal-integrity enhancement with the aid of transmit supply regulation. In contrast to their differential nature, this paper introduces a single-ended NGS transceiver that achieves 6.4Gb/s R/W operations with the aid of low-power equalization and in-situ reference-voltage calibration over a 3.5" total FR4 PCB routing with more than 25mm of package traces in a dual-rank DIMM Memory Interface system.

  • a tri modal 20 gbps link differential ddr3 gddr5 Memory Interface
    IEEE Journal of Solid-state Circuits, 2012
    Co-Authors: Kambiz Kaviani, J. Wei, T.j. Chin, Jie Shen, W T Beyene, Amir Amirkhany, Catherine Chen, Chintan Thakkar, Norman Chan, Bing Ren Chuang
    Abstract:

    This paper describes a tri-modal asymmetric bidirectional differential Memory Interface that supports data rates of up to 20 Gbps over 3" FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The Interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and high-speed tri-modal Interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor intersymbol interference (ISI) mitigation. In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the Memory. In contrast, during a Memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the Memory. The prototype tri-modal Interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 2.5 × energy-efficient Memory transactions at 16 Gbps compared to a previous single-mode generation.

  • a tri modal 20gbps link differential ddr3 gddr5 Memory Interface
    Symposium on VLSI Circuits, 2011
    Co-Authors: Kambiz Kaviani, J. Wei, T.j. Chin, Jie Shen, W T Beyene, Amir Amirkhany, Catherine Chen, Deborah Dressler, Vijay Gadde, C Huang
    Abstract:

    An improved asymmetric bidirectional Memory Interface [1] implemented in 40-nm CMOS process achieves 20Gbps per data link, and can also communicate with DDR3 and GDDR5 DRAM at 1.6Gbps and 6.4Gbps, respectively. The low-power tri-modal high-speed Interface is enabled by a continuous 1.6GHz to 10GHz clock generation mechanism, and substantial reuse of the circuit elements between the signaling modes, particularly at the driver output stage. In the high speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE to the Memory, while in Memory READ it uses a linear equalizer (LEQ) with 3dB of peaking as well as a calibrated 1-tap predictive decision feedback equalizer (prDFE). The Interface consisting of 16 data links achieves efficiency of better than 5.3mW/Gbps.

  • A tri-modal 20Gbps/link differential/DDR3/GDDR5 Memory Interface
    2011
    Co-Authors: Kambiz Kaviani, Wendemagegnehu T. Beyene, J. Wei, T.j. Chin, Jie Shen, Amir Amirkhany, Catherine Chen, Deborah Dressler, Vijay Gadde
    Abstract:

    An improved asymmetric bidirectional Memory Interface [1] implemented in 40-nm CMOS process achieves 20Gbps per data link, and can also communicate with DDR3 and GDDR5 DRAM at 1.6Gbps and 6.4Gbps, respectively. The low-power tri-modal high-speed Interface is enabled by a continuous 1.6GHz to 10GHz clock generation mechanism, and substantial reuse of the circuit elements between the signaling modes, particularly at the driver output stage. In the high speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE to the Memory, while in Memory READ it uses a linear equalizer (LEQ) with 3dB of peaking as well as a calibrated 1-tap predictive decision feedback equalizer (prDFE). The Interface consisting of 16 data links achieves efficiency of better than 5.3mW/Gbps.

Michael Bucher - One of the best experts on this subject based on the ideXlab platform.

  • ISSCC - A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
    IEEE Journal of Solid-State Circuits, 2014
    Co-Authors: Michael Bucher, Ravi Kollipara, Liji Gopalakrishnan, Pravin Kumar Venkatesan, Barry Daly, Kambiz Kaviani, Kashinath Prabhu, B. William F. Stonecypher, Wayne Dettloff
    Abstract:

    The emergence of cloud computing has driven the demand for high-density, low-latency and high-speed Memory Interfaces. For such applications the use of multiple dual-inline Memory modules (DIMMs) with multiple ranks enables time-efficient processing of high-volume data. However, the deterioration of the channel frequency response due to the presence of DIMM connectors and multiple ranks makes it challenging to perform low-power read and write (R/W) operations at high-speed. Recent works have demonstrated the use of near-ground signaling (NGS) for low-power operation and signal-integrity enhancement with the aid of transmit supply regulation. In contrast to their differential nature, this paper introduces a single-ended NGS transceiver that achieves 6.4Gb/s R/W operations with the aid of low-power equalization and in-situ reference-voltage calibration over a 3.5" total FR4 PCB routing with more than 25mm of package traces in a dual-rank DIMM Memory Interface system.

  • a 6 4 gb s near ground single ended transceiver for dual rank dimm Memory Interface systems
    International Solid-State Circuits Conference, 2013
    Co-Authors: Michael Bucher, Ravi Kollipara, Liji Gopalakrishnan, Pravin Kumar Venkatesan, Barry Daly, Kambiz Kaviani, Kashinath Prabhu, William B F Stonecypher, Wayne Dettloff, Teva Stone
    Abstract:

    The emergence of cloud computing has driven the demand for high-density, low-latency and high-speed Memory Interfaces. For such applications the use of multiple dual-inline Memory modules (DIMMs) with multiple ranks enables time-efficient processing of high-volume data. However, the deterioration of the channel frequency response due to the presence of DIMM connectors and multiple ranks makes it challenging to perform low-power read and write (R/W) operations at high-speed. Recent works have demonstrated the use of near-ground signaling (NGS) for low-power operation and signal-integrity enhancement with the aid of transmit supply regulation. In contrast to their differential nature, this paper introduces a single-ended NGS transceiver that achieves 6.4Gb/s R/W operations with the aid of low-power equalization and in-situ reference-voltage calibration over a 3.5" total FR4 PCB routing with more than 25mm of package traces in a dual-rank DIMM Memory Interface system.

  • a 4 3 gb s mobile Memory Interface with power efficient bandwidth scaling
    IEEE Journal of Solid-state Circuits, 2010
    Co-Authors: Brian S. Leibowitz, Yohan Frans, Robert E. Palmer, John W. Poulton, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Michael Bucher, Trey Greer
    Abstract:

    This paper presents a 4.3 GB/s mobile Memory Interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The Memory controller forwards a half bit-rate clock to the Memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic Interface power on the Memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the Memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

  • a 4 3gb s mobile Memory Interface with power efficient bandwidth scaling
    Symposium on VLSI Circuits, 2009
    Co-Authors: Robert E. Palmer, Yohan Frans, John W. Poulton, Brian S. Leibowitz, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Trey Greer, Michael Bucher
    Abstract:

    A 4.3GB/s mobile Memory Interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller Interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.

Yohan Frans - One of the best experts on this subject based on the ideXlab platform.

  • Design challenges of low-power and high-speed Memory Interface in advanced CMOS technology
    2011
    Co-Authors: Yohan Frans, R. Schmitt, Nhat Nguyen, Sunil Bhardwaj, Gary B. Bronner
    Abstract:

    Design requirements for low-power and high-speed Memory Interfaces in mobile systems are discussed within the context of CMOS process scaling. Key challenges include process variations, low Vdd/Vth ratio, interconnect parasitics, and model accuracy of key process parameters. It is shown that careful system architecture along with appropriate circuit techniques allow mobile Memory Interface to meet aggressive performance and power targets with conventional technology.

  • a 4 3 gb s mobile Memory Interface with power efficient bandwidth scaling
    IEEE Journal of Solid-state Circuits, 2010
    Co-Authors: Brian S. Leibowitz, Yohan Frans, Robert E. Palmer, John W. Poulton, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Michael Bucher, Trey Greer
    Abstract:

    This paper presents a 4.3 GB/s mobile Memory Interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The Memory controller forwards a half bit-rate clock to the Memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic Interface power on the Memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the Memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

  • design and characterization of a 12 8gb s low power differential Memory system for mobile applications
    Electrical Performance of Electronic Packaging, 2009
    Co-Authors: Sam Chang, Yohan Frans, R. Schmitt, Chris Madden, Joong-ho Kim, Brian S. Leibowitz, Chuck Yuan Fred Ware, Nhat Nguyen
    Abstract:

    This paper describes the design and characterization of a low power differential Memory Interface targeted for mobile applications. The initial design of the Memory Interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 Memory Interface based on single-ended signaling, the differential Memory Interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the Memory system performance and to validate the Memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.

  • A 4.3GB/s mobile Memory Interface with power-efficient bandwidth scaling
    2009
    Co-Authors: Robert E. Palmer, Yohan Frans, John W. Poulton, Brian S. Leibowitz, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Trey Greer
    Abstract:

    A 4.3GB/s mobile Memory Interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller Interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.

  • a 4 3gb s mobile Memory Interface with power efficient bandwidth scaling
    Symposium on VLSI Circuits, 2009
    Co-Authors: Robert E. Palmer, Yohan Frans, John W. Poulton, Brian S. Leibowitz, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Trey Greer, Michael Bucher
    Abstract:

    A 4.3GB/s mobile Memory Interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller Interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.

Brian S. Leibowitz - One of the best experts on this subject based on the ideXlab platform.

  • a 4 3 gb s mobile Memory Interface with power efficient bandwidth scaling
    IEEE Journal of Solid-state Circuits, 2010
    Co-Authors: Brian S. Leibowitz, Yohan Frans, Robert E. Palmer, John W. Poulton, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Michael Bucher, Trey Greer
    Abstract:

    This paper presents a 4.3 GB/s mobile Memory Interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The Memory controller forwards a half bit-rate clock to the Memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic Interface power on the Memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the Memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

  • design and characterization of a 12 8gb s low power differential Memory system for mobile applications
    Electrical Performance of Electronic Packaging, 2009
    Co-Authors: Sam Chang, Yohan Frans, R. Schmitt, Chris Madden, Joong-ho Kim, Brian S. Leibowitz, Chuck Yuan Fred Ware, Nhat Nguyen
    Abstract:

    This paper describes the design and characterization of a low power differential Memory Interface targeted for mobile applications. The initial design of the Memory Interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 Memory Interface based on single-ended signaling, the differential Memory Interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the Memory system performance and to validate the Memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.

  • A 4.3GB/s mobile Memory Interface with power-efficient bandwidth scaling
    2009
    Co-Authors: Robert E. Palmer, Yohan Frans, John W. Poulton, Brian S. Leibowitz, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Trey Greer
    Abstract:

    A 4.3GB/s mobile Memory Interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller Interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.

  • a 4 3gb s mobile Memory Interface with power efficient bandwidth scaling
    Symposium on VLSI Circuits, 2009
    Co-Authors: Robert E. Palmer, Yohan Frans, John W. Poulton, Brian S. Leibowitz, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Trey Greer, Michael Bucher
    Abstract:

    A 4.3GB/s mobile Memory Interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller Interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.

  • a 16 gb s link 64 gb s bidirectional asymmetric Memory Interface
    IEEE Journal of Solid-state Circuits, 2009
    Co-Authors: Hae-chang Lee, Yohan Frans, Nhat Nguyen, Kambiz Kaviani, Jung-hoon Chun, T.j. Chin, Jie Shen, Kun-yung Ken Chang, Brian S. Leibowitz, Xudong Shi
    Abstract:

    This paper describes a bidirectional, differential, 16 Gb/s per link Memory Interface that includes a Controller and an emulated DRAM physical Interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the Interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this Interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 211-1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.

Trey Greer - One of the best experts on this subject based on the ideXlab platform.

  • a 4 3 gb s mobile Memory Interface with power efficient bandwidth scaling
    IEEE Journal of Solid-state Circuits, 2010
    Co-Authors: Brian S. Leibowitz, Yohan Frans, Robert E. Palmer, John W. Poulton, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Michael Bucher, Trey Greer
    Abstract:

    This paper presents a 4.3 GB/s mobile Memory Interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The Memory controller forwards a half bit-rate clock to the Memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic Interface power on the Memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the Memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

  • A 4.3GB/s mobile Memory Interface with power-efficient bandwidth scaling
    2009
    Co-Authors: Robert E. Palmer, Yohan Frans, John W. Poulton, Brian S. Leibowitz, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Trey Greer
    Abstract:

    A 4.3GB/s mobile Memory Interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller Interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.

  • a 4 3gb s mobile Memory Interface with power efficient bandwidth scaling
    Symposium on VLSI Circuits, 2009
    Co-Authors: Robert E. Palmer, Yohan Frans, John W. Poulton, Brian S. Leibowitz, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, Trey Greer, Michael Bucher
    Abstract:

    A 4.3GB/s mobile Memory Interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller Interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.