The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Angelos Bilas - One of the best experts on this subject based on the ideXlab platform.
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CableS: Thread control and Memory Management extensions for shared virtual Memory clusters
Proceedings - International Symposium on High-Performance Computer Architecture, 2002Co-Authors: P. Jamieson, Angelos BilasAbstract:Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although clusters have many advantages, their applicability in emerging areas of applications has been limited. One of the main reasons for this is the fact that clusters do not provide a single system image and thus are hard to program. In this work we address this problem by providing a single-cluster image with respect to thread and Memory Management. We implement our system, CableS (Cluster enabled threads), on a 32-processor cluster interconnected with a low-latency, high-bandwidth system area network and conduct an early exploration of the costs involved in providing the extra functionality. We demonstrate the versatility :of Cables with a wide range of applications and show that clusters can be used to support applications that have been written for more expensive tightly-coupled systems, With very little effort on the programmer side: (a) We run legacy pthreads applications without any major modifications. (b) We use a public domain OpenMP compiler (OdinMP) to translate OpenMP programs to pthreads and execute them on our system, with no or few modifications to the translated pthreads source code. (c) We provide an implementation of the M4 macros for our pthreads system and run the SPLASH-2 applications. We also show that the overhead introduced by the extra functionality of CableS affects the parallel section of applications that have been tuned for the shared Memory abstraction only in cases where the data placement is affected by operating system (WindowsNT) limitations in virtual Memory mappings granularity.
Mads Tofte - One of the best experts on this subject based on the ideXlab platform.
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a retrospective on region based Memory Management
Higher-Order and Symbolic Computation archive, 2004Co-Authors: Mads Tofte, Lars Birkedal, Martin Elsman, Niels HallenbergAbstract:We report on our experience with designing, implementing, proving correct, and evaluating a region-based Memory Management system.
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region based Memory Management
Information & Computation, 1997Co-Authors: Mads Tofte, Jeanpierre TalpinAbstract:This paper describes a Memory Management discipline for programs that perform dynamic Memory allocation and de-allocation. At runtime, all values are put intoregions. The store consists of a stack of regions. All points of region allocation and de-allocation are inferred automatically, using a type and effect based program analysis. The scheme does not assume the presence of a garbage collector. The scheme was first presented in 1994 (M. Tofte and J.-P. Talpin,in“Proceedings of the 21st ACM SIGPLAN?SIGACT Symposium on Principles of Programming Languages,” pp. 188?201); subsequently, it has been tested in The ML Kit with Regions, a region-based, garbage-collection free implementation of the Standard ML Core language, which includes recursive datatypes, higher-order functions and updatable references L. Birkedal, M. Tofte, and M. Vejlstrup, (1996),in“Proceedings of the 23 rd ACM SIGPLAN?SIGACT Symposium on Principles of Programming Languages,” pp. 171?183. This paper defines a region-based dynamic semantics for a skeletal programming language extracted from Standard ML. We present the inference system which specifies where regions can be allocated and de-allocated and a detailed proof that the system is sound with respect to a standard semantics. We conclude by giving some advice on how to write programs that run well on a stack of regions, based on practical experience with the ML Kit.
Trishul Chilimbi - One of the best experts on this subject based on the ideXlab platform.
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Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management
2016Co-Authors: Vivek Seshadri, Onur Mutlu, Gennady Pekhimenko, Olatunji Ruwase, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing Memory at a Vne (e.g., cache line) granularity—e.g., Vne-grained deduplication and Vne-grained Memory protection. Unfortunately, existing vir-tual Memory systems track Memory at a larger granularity (e.g., 4 KB pages), inhibiting eXcient implementation of such techniques. Simply reducing the page size results in an unac-ceptable increase in page table overhead and TLB pressure. We propose a new virtual Memory framework that enables eXcient implementation of a variety of Vne-grained Memory Management techniques. In our framework, each virtual page can be mapped to a structure called a page overlay, in addi-tion to a regular physical page. An overlay contains a subset of cache lines from the virtual page. Cache lines that are presen
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page overlays an enhanced virtual Memory framework to enable fine grained Memory Management
International Symposium on Computer Architecture, 2015Co-Authors: Vivek Seshadri, Onur Mutlu, Gennady Pekhimenko, Olatunji Ruwase, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing Memory at a fine (e.g., cache line) granularity---e.g., fine-grained deduplication and fine-grained Memory protection. Unfortunately, existing virtual Memory systems track Memory at a larger granularity (e.g., 4 KB pages), inhibiting efficient implementation of such techniques. Simply reducing the page size results in an unacceptable increase in page table overhead and TLB pressure. We propose a new virtual Memory framework that enables efficient implementation of a variety of fine-grained Memory Management techniques. In our framework, each virtual page can be mapped to a structure called a page overlay, in addition to a regular physical page. An overlay contains a subset of cache lines from the virtual page. Cache lines that are present in the overlay are accessed from there and all other cache lines are accessed from the regular physical page. Our page-overlay framework enables cache-line-granularity Memory Management without significantly altering the existing virtual Memory framework or introducing high overheads. We show that our framework can enable simple and efficient implementations of seven Memory Management techniques, each of which has a wide variety of applications. We quantitatively evaluate the potential benefits of two of these techniques: overlay-on-write and sparse-data-structure computation. Our evaluations show that overlay-on-write, when applied to fork, can improve performance by 15% and reduce Memory capacity requirements by 53% on average compared to traditional copy-on-write. For sparse data computation, our framework can outperform a state-of-the-art software-based sparse representation on a number of real-world sparse matrices. Our framework is general, powerful, and effective in enabling fine-grained Memory Management at low cost.
Saswati Sarkar - One of the best experts on this subject based on the ideXlab platform.
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optimum scheduling and Memory Management in input queued switches with finite buffer space
IEEE Transactions on Information Theory, 2004Co-Authors: Saswati SarkarAbstract:The goal of this paper is to design optimal scheduling and Memory Management so as to minimize packet loss in input queued switches with finite input buffers. The contribution is to obtain closed-form optimal strategies that minimize packet loss in 2/spl times/2 switches with equal arrival rates for all streams. For arbitrary arrival rates, the contribution is to identify certain characteristics of the optimal strategy, and use these characteristics to design a near-optimal heuristic. A lower bound for the cost associated with packet loss for N/spl times/N switches is obtained. This lower bound is used to design a heuristic which attains near-minimum packet loss in N/spl times/N switches with arbitrary N. These policies reduce packet loss by about 25% as compared to the optimal strategy for the infinite buffer case. The framework and the policies proposed here apply to buffer-constrained wireless networks as well.
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optimum scheduling and Memory Management in input queued switches with finite buffer space
International Conference on Computer Communications, 2003Co-Authors: Saswati SarkarAbstract:This paper addresses scheduling and Memory Management in input queued switches with finite input buffers, with the objective of minimizing packet loss. The framework and algorithms proposed here apply to buffer constrained wireless networks as well. The scheduling problem has been extensively addressed under the assumption of infinite input buffers. We study the finite buffer case here which arises in practice. The introduction of Memory constraint significantly complicates the problem. The optimal strategies for infinite buffer case no longer apply and become strictly suboptimal in presence of Memory limitations. We present closed form optimal strategies which minimize packet loss in 2 × 2 switches with equal arrival rates for all streams. We identify certain characteristics of the optimal strategy for arbitrary arrival rates, and use these properties to design a near optimal heuristic. We use the insight obtained from the investigation for 2 × 2 switches to propose a heuristic for N × N switches, arbitrary N and show numerically that this strategy performs close to optimal. The policies presented here reduce packet loss by about 25% as compared to the optimal strategy for the infinite buffer case.
Akinori Yonezawa - One of the best experts on this subject based on the ideXlab platform.
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region based Memory Management for a dynamically typed language
Asian Symposium on Programming Languages and Systems, 2004Co-Authors: Akihito Nagata, N. Kobayashi, Akinori YonezawaAbstract:Region-based Memory Management scheme has been proposed for the programming language ML. In this scheme, a compiler statically estimates the lifetime of each object by performing an extension of type inference (called region inference) and inserts code for Memory allocation and deallocation. Advantages of this scheme are that Memory objects can be deallocated safely (unlike with manual Memory Management using malloc/free) and often earlier than with run-time garbage collection. Since the region inference is an extension of the ML type inference, however, it was not clear whether the region-based Memory Management was applicable to dynamically-typed programming languages like Scheme. In this paper, we show that the region-based Memory Management can be applied to dynamically-typed languages by combining region inference and Cartwright et al.’s soft type system.