The Experts below are selected from a list of 1437 Experts worldwide ranked by ideXlab platform

D W Boerstler - One of the best experts on this subject based on the ideXlab platform.

  • a clock distribution network for Microprocessors
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: P.j. Restle, T G Mcnamara, D A Webber, P J Camporese, K F Eng, M J Rohn, M P Quaranta, Keith A. Jenkins, D.h. Allen, D W Boerstler
    Abstract:

    A global clock distribution strategy used on several Microprocessor Chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large Microprocessor Chips has been measured.

  • A clock distribution network for Microprocessors
    2000 Symposium on VLSI Circuits Digest of Technical Papers Cat No00CH37103, 2000
    Co-Authors: P.j. Restle, T G Mcnamara, D A Webber, P J Camporese, K F Eng, M J Rohn, M P Quaranta, Keith A. Jenkins, D.h. Allen, D W Boerstler
    Abstract:

    A global clock distribution strategy implemented on several Microprocessor Chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 m of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large Microprocessor Chips

M Sanquer - One of the best experts on this subject based on the ideXlab platform.

  • a cmos silicon spin qubit
    Nature Communications, 2016
    Co-Authors: Romain Maurand, X Jehl, Dharmraj Kotekarpatil, A Corna, H Bohuslavskyi, R Lavieville, Louis Hutin, Sylvain Barraud, Maud Vinet, M Sanquer
    Abstract:

    Silicon, the main constituent of Microprocessor Chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. Silicon is a promising material for realization of quantum processors, particularly as it could be naturally integrated with classical control hardware based on CMOS technology. Here the authors report a silicon qubit device made with an industry-standard fabrication process on a CMOS platform.

P.j. Restle - One of the best experts on this subject based on the ideXlab platform.

  • a clock distribution network for Microprocessors
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: P.j. Restle, T G Mcnamara, D A Webber, P J Camporese, K F Eng, M J Rohn, M P Quaranta, Keith A. Jenkins, D.h. Allen, D W Boerstler
    Abstract:

    A global clock distribution strategy used on several Microprocessor Chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large Microprocessor Chips has been measured.

  • A clock distribution network for Microprocessors
    2000 Symposium on VLSI Circuits Digest of Technical Papers Cat No00CH37103, 2000
    Co-Authors: P.j. Restle, T G Mcnamara, D A Webber, P J Camporese, K F Eng, M J Rohn, M P Quaranta, Keith A. Jenkins, D.h. Allen, D W Boerstler
    Abstract:

    A global clock distribution strategy implemented on several Microprocessor Chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 m of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large Microprocessor Chips

Romain Maurand - One of the best experts on this subject based on the ideXlab platform.

  • a cmos silicon spin qubit
    Nature Communications, 2016
    Co-Authors: Romain Maurand, X Jehl, Dharmraj Kotekarpatil, A Corna, H Bohuslavskyi, R Lavieville, Louis Hutin, Sylvain Barraud, Maud Vinet, M Sanquer
    Abstract:

    Silicon, the main constituent of Microprocessor Chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. Silicon is a promising material for realization of quantum processors, particularly as it could be naturally integrated with classical control hardware based on CMOS technology. Here the authors report a silicon qubit device made with an industry-standard fabrication process on a CMOS platform.

T G Mcnamara - One of the best experts on this subject based on the ideXlab platform.

  • a clock distribution network for Microprocessors
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: P.j. Restle, T G Mcnamara, D A Webber, P J Camporese, K F Eng, M J Rohn, M P Quaranta, Keith A. Jenkins, D.h. Allen, D W Boerstler
    Abstract:

    A global clock distribution strategy used on several Microprocessor Chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large Microprocessor Chips has been measured.

  • A clock distribution network for Microprocessors
    2000 Symposium on VLSI Circuits Digest of Technical Papers Cat No00CH37103, 2000
    Co-Authors: P.j. Restle, T G Mcnamara, D A Webber, P J Camporese, K F Eng, M J Rohn, M P Quaranta, Keith A. Jenkins, D.h. Allen, D W Boerstler
    Abstract:

    A global clock distribution strategy implemented on several Microprocessor Chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 m of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large Microprocessor Chips