The Experts below are selected from a list of 123 Experts worldwide ranked by ideXlab platform

Harry Athanassiadis - One of the best experts on this subject based on the ideXlab platform.

  • testing interrupts having a service priority order by applying different interrupt priority levels
    2001
    Co-Authors: Harry Athanassiadis
    Abstract:

    A test of interrupts in a Microprocessor System having a number of interrupt sources which are associated with a memory and assigned a default priority level and a position in a service order. In operation requests for service from the interrupt sources will be processed by calling the interrupt service routine of the interrupt request having the highest priority level or in the event that interrupt requests are at the same priority level are received the interrupt requests will be serviced from first in the service order to last in the service order. The testing mechanism comprises applying an array of priority levels (priority window) to some of the interrupt request lines and enabling all other interrupt requests at their default priority level simultaneously. A value from a global counter is then applied to the memory associated with the interrupt source which is to be serviced. This global counter is then incremented by one and the array of priority values is shifted along the service order from last in the service order to first for successive tests until the test is complete (figure 2b). The values stored in the memories associated with each interrupt source are then compared to a pre-arranged sequence of expected values to determine if an error has occurred in the Microprocessor interrupts.

  • testing interrupts having a service priority order by applying combinations of interrupt priority levels
    2001
    Co-Authors: Harry Athanassiadis
    Abstract:

    A test of interrupts in a Microprocessor System having a number of interrupt sources which are associated with a memory and assigned a default priority level and a position in a service order. In operation requests for service from the interrupt sources will be processed by calling the interrupt service routine of the interrupt request having the highest priority level or in the event that interrupt requests are at the same priority level are received the interrupt requests will be serviced from first in the service order to last in the service order. The testing mechanism comprises applying an array of priority levels (priority window, figure 1) except the interrupt having the highest priority to some of the interrupt request lines and enabling all other interrupt requests at their default priority level simultaneously. A value from a global counter is then applied to the memory associated with the interrupt source which is to be serviced. This global counter is then incremented by one and the test is repeated enabling all interrupts simultaneously including the interrupt having the highest priority and the value in the global counter is again applied to the memory of the interrupt to be serviced. Next the array of priority values is shifted along the service order from last in the service order to first according to a sequence for successive tests until all tests have been completed (figure 2b). The values stored in the memories associated with each interrupt source are then compared to a pre-arranged sequence of expected values to determine if an error has occurred in the Microprocessor interrupts.

Seda Ogrenci Memik - One of the best experts on this subject based on the ideXlab platform.

  • Optimizing Thermal Sensor Allocation for Microprocessors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008
    Co-Authors: Seda Ogrenci Memik, Min Ni, Rajarshi Mukherjee, Jieyi Long
    Abstract:

    High-performance Microprocessor families employ dynamic-thermal-management techniques to cope with the increasing thermal stress resulting from peaking power densities. These techniques operate on feedback generated from on-die thermal sensors. The allocation and the placement of thermal-sensing elements directly impact the effectiveness of the dynamic management mechanisms. In this paper, we propose Systematic techniques for determining the optimal locations for thermal sensors to provide high-fidelity thermal monitoring of a complex Microprocessor System. Our strategies can be divided into two main categories: uniform sensor allocation and nonuniform sensor allocation. In the uniform approach, the sensors are placed on a regular grid. The nonuniform allocation identifies an optimal physical location for each sensor such that the sensor's attraction toward steep thermal gradients is maximized, which can result in uneven concentrations of sensors on different locations of the chip. We also present a hybrid algorithm that shows the tradeoffs associated with number of sensors and expected accuracy. Our experimental results show that our uniform approach using interpolation can detect the chip temperature with a maximum error of 5.47degC and an average maximum error of 1.05degC . On the other hand, our nonuniform strategy is able to create a sensor distribution for a given Microprocessor architecture, providing thermal measurements with a maximum error of 3.18degC and an average maximum error of 1.63degC across a wide set of applications.

  • Systematic temperature sensor allocation and placement for Microprocessors
    Design Automation Conference, 2006
    Co-Authors: Rajarshi Mukherjee, Seda Ogrenci Memik
    Abstract:

    Modern high performance processors employ advanced techniques for thermal management, which rely on accurate readings of on-die thermal sensors. As the importance of thermal effects on reliability and performance of integrated circuits increases careful planning and embedding of thermal monitoring mechanisms into these Systems will be crucial. Systematic tools for analysis of thermal behavior and determination of best allocation and placement of thermal sensing elements is therefore a highly relevant problem. In this paper, we propose novel optimization techniques for determining the optimal locations and allocations for thermal sensors to provide a high fidelity thermal profile of a complex Microprocessor System. Our algorithm identifies an optimal physical location for each sensor such that the sensor's the attraction towards steep thermal gradient is maximized. We also present a hybrid allocation and placement strategy showing the trade-offs associated with number of sensors used and expected accuracy. Our results show that our tool is able to create a sensor distribution for a given Microprocessor architecture providing thermal measurements with maximum error of 3.18°C and average maximum error of 1.63°C across a wide set of applications.

Michael Franz - One of the best experts on this subject based on the ideXlab platform.

  • power reduction techniques for Microprocessor Systems
    ACM Computing Surveys, 2005
    Co-Authors: Vasanth Venkatachalam, Michael Franz
    Abstract:

    Power consumption is a major factor that limits the performance of computers. We survey the “state of the art” in techniques that reduce the total power consumed by a Microprocessor System over time. These techniques are applied at various levels ranging from circuits to architectures, architectures to System software, and System software to applications. They also include holistic approaches that will become more important over the next decade. We conclude that power management is a multifaceted discipline that is continually expanding with new techniques being developed at every level. These techniques may eventually allow computers to break through the “power wall” and achieve unprecedented levels of performance, versatility, and reliability. Yet it remains too early to tell which techniques will ultimately solve the power problem.

Rajarshi Mukherjee - One of the best experts on this subject based on the ideXlab platform.

  • Optimizing Thermal Sensor Allocation for Microprocessors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008
    Co-Authors: Seda Ogrenci Memik, Min Ni, Rajarshi Mukherjee, Jieyi Long
    Abstract:

    High-performance Microprocessor families employ dynamic-thermal-management techniques to cope with the increasing thermal stress resulting from peaking power densities. These techniques operate on feedback generated from on-die thermal sensors. The allocation and the placement of thermal-sensing elements directly impact the effectiveness of the dynamic management mechanisms. In this paper, we propose Systematic techniques for determining the optimal locations for thermal sensors to provide high-fidelity thermal monitoring of a complex Microprocessor System. Our strategies can be divided into two main categories: uniform sensor allocation and nonuniform sensor allocation. In the uniform approach, the sensors are placed on a regular grid. The nonuniform allocation identifies an optimal physical location for each sensor such that the sensor's attraction toward steep thermal gradients is maximized, which can result in uneven concentrations of sensors on different locations of the chip. We also present a hybrid algorithm that shows the tradeoffs associated with number of sensors and expected accuracy. Our experimental results show that our uniform approach using interpolation can detect the chip temperature with a maximum error of 5.47degC and an average maximum error of 1.05degC . On the other hand, our nonuniform strategy is able to create a sensor distribution for a given Microprocessor architecture, providing thermal measurements with a maximum error of 3.18degC and an average maximum error of 1.63degC across a wide set of applications.

  • Systematic temperature sensor allocation and placement for Microprocessors
    Design Automation Conference, 2006
    Co-Authors: Rajarshi Mukherjee, Seda Ogrenci Memik
    Abstract:

    Modern high performance processors employ advanced techniques for thermal management, which rely on accurate readings of on-die thermal sensors. As the importance of thermal effects on reliability and performance of integrated circuits increases careful planning and embedding of thermal monitoring mechanisms into these Systems will be crucial. Systematic tools for analysis of thermal behavior and determination of best allocation and placement of thermal sensing elements is therefore a highly relevant problem. In this paper, we propose novel optimization techniques for determining the optimal locations and allocations for thermal sensors to provide a high fidelity thermal profile of a complex Microprocessor System. Our algorithm identifies an optimal physical location for each sensor such that the sensor's the attraction towards steep thermal gradient is maximized. We also present a hybrid allocation and placement strategy showing the trade-offs associated with number of sensors used and expected accuracy. Our results show that our tool is able to create a sensor distribution for a given Microprocessor architecture providing thermal measurements with maximum error of 3.18°C and average maximum error of 1.63°C across a wide set of applications.

Trevor Pering - One of the best experts on this subject based on the ideXlab platform.

  • voltage scheduling in the iparm Microprocessor System
    International Symposium on Low Power Electronics and Design, 2000
    Co-Authors: Trevor Pering, Thomas D Burd, R W Brodersen
    Abstract:

    Microprocessors represent a significant portion of the energy con?sumed in portable electronic devices. Dynamic Voltage Scaling (DVS) allows a device to reduce energy consumption by lowering its processor speed at run-time, allowing a corresponding reduction in processor voltage and energy. A voltage scheduler determines the appropriate operating voltage by analyzing application con?straints and requirements. A complete software implementation, including both applications and the underlying operating System, shows that DVS is effective at reducing the energy consumed with?out requiring extensive software modification.

  • a dynamic voltage scaled Microprocessor System
    International Solid-State Circuits Conference, 2000
    Co-Authors: Thomas D Burd, Trevor Pering, A J Stratakos, R W Brodersen
    Abstract:

    The Microprocessor System in portable electronic devices often has a time-varying computational load which is comprised of: (1) compute-intensive and low-latency processes, (2) background and high-latency processes, and (3) System idle. The key design objectives for the processor Systems in these applications are providing the highest possible peak performance for the compute-intensive code (e.g., handwriting recognition, image decompression) while maximizing the battery life for the remaining low performance periods. If clock frequency and supply voltage are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required. This strategy, which achieves the highest possible energy efficiency for time-varying computational loads, is called dynamic voltage scaling (DVS).

  • dynamic voltage scaling and the design of a low power Microprocessor System
    1998
    Co-Authors: Trevor Pering, Tom Burd
    Abstract:

    This paper describes the design of a low-power Microprocessor System that can run between 8Mhz at 1.1V and 100MHz at 3.3V. The ramifications of Dynamic Voltage Scaling, which allows the processor to dynamically alter its operating voltage at run-time, will be presented along with a description of the System design and an approach to benchmarking. In addition, a more in-depth discussion of the cache memory System will be