The Experts below are selected from a list of 144816 Experts worldwide ranked by ideXlab platform

Gordon W. Roberts - One of the best experts on this subject based on the ideXlab platform.

  • ISCAS - Wide linear range voltage-controlled delay unit for time-Mode Signal processing
    2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015
    Co-Authors: Soheyl Ziabakhsh, Ghyslain Gagnon, Gordon W. Roberts
    Abstract:

    A voltage-controlled delay unit (VCDU) for low-voltage time-Mode Signal processing is presented in this paper. The proposed VCDU uses a Signal conditioning circuit to achieve wider-range and higher linearity than state-of-the-art VCDUs. Circuit-level simulations in 0.18μm CMOS process show a linearity error of less than ± 0.2% for a 0.15 V to 1 V input range. The proposed VCDU consumes 315 μW from a 1.8 V supply at its maximum sampling frequency of 500 MHz. The proposed VCDU is validated in a first-order time-Mode ΔΣ modulator application. Circuit-level simulation results of the ΔΣ modulator show a peak SNDR of 58 dB when clocked at 140 MHz with a 400 kHz bandwidth.

  • All-digital Time-Mode elliptic filters based on the operational simulation of LC ladders
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Moataz Abdelfattah, Gordon W. Roberts, Vamsy P. Chodavarapu
    Abstract:

    Time-Mode Signal Processing (TMSP) techniques are attempting to develop analog Signal processing algorithms using primitive digital building blocks such as inverters and NAND/NOR gates. By doing so, the design of such analog circuits can be captured and automated by standard digital design tools and methodologies. In this paper, a method is proposed for designing high-order elliptic filters based on the operational simulation of LC ladder networks using a set of all-digital timeMode building blocks (some new, some known). The design of a fifth-order elliptic filter having 1 dB passband ripple and 60 dB of stopband attenuation will be used to demonstrate the feasibility of the proposed design method.

  • ISCAS - All-digital Time-Mode elliptic filters based on the operational simulation of LC ladders
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Moataz Abdelfattah, Gordon W. Roberts, Vamsy P. Chodavarapu
    Abstract:

    Time-Mode Signal Processing (TMSP) techniques are attempting to develop analog Signal processing algorithms using primitive digital building blocks such as inverters and NAND/NOR gates. By doing so, the design of such analog circuits can be captured and automated by standard digital design tools and methodologies. In this paper, a method is proposed for designing high-order elliptic filters based on the operational simulation of LC ladder networks using a set of all-digital timeMode building blocks (some new, some known). The design of a fifth-order elliptic filter having 1 dB passband ripple and 60 dB of stopband attenuation will be used to demonstrate the feasibility of the proposed design method.

  • ISCAS - Reducing the analog-digital productivity gap using time-Mode Signal processing
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Gordon W. Roberts
    Abstract:

    The productivity gap between analog and digital circuit design has been steadily increasingly over the past four decades of semiconductor development, largely driven by advances in digital CAD. Using a simple design productivity metric, like the number of transistor utilized per man-months for any given design, the analog team can incorporate anywhere between 10 - 100 transistors per man-months whereas the digital design team can utilize 100's of thousands or more per man-months. It is the objective of this paper to describe how time-Mode Signal processing can be used to reduce the analog-digital productivity gap and, in addition, consider how time-Mode Signal processing can assist with manufacturing considerations like analog/mixed-Signal production test.

  • Sampled-data IIR filtering via time-Mode Signal processing
    Analog Integrated Circuits and Signal Processing, 2011
    Co-Authors: Michael M. Guttman, Gordon W. Roberts
    Abstract:

    In this work, the design of sampled-data infinite impulse response (IIR) filters based on time-Mode Signal processing (TMSP) circuits is presented. Time-Mode Signal processing, defined as the processing of sampled analog information using time-difference variables, is still a relatively new technology, and therefore, there is still much development needed to extend the technology into a general Signal-processing tool. In this work, a set of general building blocks will be introduced that perform the most basic mathematical operations in the time-Mode. By arranging these basic structures, higher-order time-Mode systems, specifically, time-Mode IIR filters, will be realized. A second low-pass time-Mode IIR filter is implemented using discrete components. Measured results confirmed that the circuit performed low-pass filtering, providing a maximum SNR of 45.2 dB and SNDR of 35.3 dB.

H Ontrop - One of the best experts on this subject based on the ideXlab platform.

  • current Mode techniques for high speed vlsi circuits with application to current sense amplifier for cmos sram s
    IEEE Journal of Solid-state Circuits, 1991
    Co-Authors: Evert Seevinck, P J Van Beers, H Ontrop
    Abstract:

    The speed of VLSI chips is increasingly limited by Signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-Mode rather than conventional voltage-Mode Signal transporting techniques. The key to this approach is the use of low-resistance current-Signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access. >

S Shimizu - One of the best experts on this subject based on the ideXlab platform.

  • high speed cmos i o buffer circuits
    IEEE Journal of Solid-state Circuits, 1992
    Co-Authors: Motomi Ishibe, Shoji Otaka, K J Takeda, Yasushi Toyoshima, Sumiko Takatsuka, Sumio Tanaka, S Shimizu
    Abstract:

    Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. An all-CMOS set of I/O buffer circuits, which use current-Mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates is described. The circuits are also compatible with voltage-Mode Signal levels for ECL input and MOS output circuits. >

Evert Seevinck - One of the best experts on this subject based on the ideXlab platform.

  • current Mode techniques for high speed vlsi circuits with application to current sense amplifier for cmos sram s
    IEEE Journal of Solid-state Circuits, 1991
    Co-Authors: Evert Seevinck, P J Van Beers, H Ontrop
    Abstract:

    The speed of VLSI chips is increasingly limited by Signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-Mode rather than conventional voltage-Mode Signal transporting techniques. The key to this approach is the use of low-resistance current-Signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access. >

G W Roberts - One of the best experts on this subject based on the ideXlab platform.

  • all digital time Mode direct form all pole biquadratic filter realization
    IEEE Transactions on Circuits and Systems Ii-express Briefs, 2017
    Co-Authors: Moataz Abdelfattah, G W Roberts
    Abstract:

    In this brief, the design of time-Mode Signal processing (TMSP) circuits having an all-digital advantage is introduced and experimental data covering all necessary aspects of operation such as frequency response are presented. TMSP building blocks were used to design two second-order filter prototypes having Butterworth and Chebychev I responses demonstrating peak Signal-to-noise-plus-distortion values of 47 dB and 37 dB, respectively, making it a good candidate for data conversion applications.

  • delta sigma a d conversion via time Mode Signal processing
    IEEE Transactions on Circuits and Systems I-regular Papers, 2009
    Co-Authors: Christopher Taillefer, G W Roberts
    Abstract:

    In this paper, a Signal processing methodology is proposed that performs delta-sigma (DeltaSigma) analog-to-digital (A/D) conversion on voltage Signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-Mode (TM) Signal processing, uses time-difference variables as an intermediate Signal between the input voltage and the digital output. The resulting low-cost silicon devices offer very compact, low-power, high-speed, and robust A/D converter (ADC) alternatives. A first-order DeltaSigma ADC is implemented using this methodology. Two ICs were fabricated in a 0.18- mum CMOS technology to demonstrate the feasibility of the TM DeltaSigma ADC approach. The first IC implements a single-ended input design while a differential design was fabricated in the second IC. Experimental results reveal that these devices can achieve 7-9-bit resolutions within 125-400-kHz bandwidths, while occupying areas smaller than 50 mum t50 mum and consuming less than 800 muW.