MPEG2

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Isao Shirakawa - One of the best experts on this subject based on the ideXlab platform.

  • Implementation of half-pel precision motion estimator for MPEG2 MP@HL
    Proceedings of Digital Processing Applications (TENCON '96), 1996
    Co-Authors: Fujita, Takao Onoye, Isao Shirakawa, Shuji Tsukiyama, K. Matsumura
    Abstract:

    A half-pel precision single chip motion estimator is described dedicatedly for MPEG2 MP@HL moving pictures. Adopting a two-level hierarchical searching algorithm and the maximum possible reuse mechanism of reference pixels, MP@HL motion estimation is successfully facilitated. The broadcasting type PE array is used both for integer-pel precision vector and half-pel precision vector search processes. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip, which contains 1450 K transistors on a 12.7/spl times/13.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables real time motion estimation for MPEG2 MP@HL.

  • Architecture for MPEG2 MP@HL real time motion estimator
    1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, 1996
    Co-Authors: Takao Onoye, Fujita, Isao Shirakawa, K. Matsumura, Hiromu Ariyoshi, Shuji Tsukiyama
    Abstract:

    A VLSI architecture of a motion estimator is proposed, dedicated to MPEG2 MP@HL, which adopts a two-level hierarchical searching algorithm in detecting motion vectors. A novel mechanism is introduced into the full-search procedure which attempts the maximum possible reuse of reference pixels to reduce the bandwidth of frame memory interface. The proposed architecture has been integrated into a 0.6 /spl mu/m triple-metal CMOS chip which contains 1200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.

  • VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL
    Proceedings of Custom Integrated Circuits Conference, 1996
    Co-Authors: Takao Onoye, Fujita, Isao Shirakawa, K. Matsumura, Hiromu Ariyoshi, Shuji Tsukiyama
    Abstract:

    A VLSI motion estimator dedicated to MPEG2 MP@HL has been developed. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip which contains 1,200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.

  • hdtv level MPEG2 video decoder vlsi
    International Conference on Microelectronics, 1995
    Co-Authors: Takao Onoye, Toshihiro Masaki, Yasuo Morimoto, Yoh Sato, Isao Shirakawa
    Abstract:

    A novel architecture for an HDTV level MPEG2 decoder is developed, which consists of specific functional macrocells and macroblock level pipeline buffers. Owing to the sophisticated I/O interface among macrocells, macroblock level pipeline buffers are successfully incorporated with functional macrocells. A new organization of frame memory and interface is also devised. The designed decoder contains 454 K transistors, and occupies 81.0 mm/sup 2/ with a 0.6 /spl mu/m triple-metal CMOS technology.

  • vlsi implementation of inverse discrete cosine transformer and motion compensator for MPEG2 hdtv video decoding
    IEEE Transactions on Circuits and Systems for Video Technology, 1995
    Co-Authors: Toshihiro Masaki, Takao Onoye, Yasuo Morimoto, Isao Shirakawa
    Abstract:

    An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm/sup 2/ by a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock within 3.84 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) images in real time. >

Panos Nasiopoulos - One of the best experts on this subject based on the ideXlab platform.

  • ICIP - An Efficient MPEG2 to H.264 Half-Pixel Motion Compensation Transcoding
    2006 International Conference on Image Processing, 2006
    Co-Authors: Qiang Tang, Rabab K Ward, Panos Nasiopoulos
    Abstract:

    An efficient MPEG2 to H.264 half-pixel motion compensation transcoding method is proposed. The Inter macroblock transcoding is implemented in the transform domain. An algorithm is designed to compensate for the errors which arise because of the different half-pixel interpolation procedures used by MPEG2 and H.264/AVC. The experimental results show that the PSNR values of the transcoded H.264 streams result in significant improvement (average 5.5 dB) after we reduce the half-pixel interpolation errors.

  • an efficient MPEG2 to h 264 half pixel motion compensation transcoding
    International Conference on Image Processing, 2006
    Co-Authors: Qiang Tang, Rabab K Ward, Panos Nasiopoulos
    Abstract:

    An efficient MPEG2 to H.264 half-pixel motion compensation transcoding method is proposed. The Inter macroblock transcoding is implemented in the transform domain. An algorithm is designed to compensate for the errors which arise because of the different half-pixel interpolation procedures used by MPEG2 and H.264/AVC. The experimental results show that the PSNR values of the transcoded H.264 streams result in significant improvement (average 5.5 dB) after we reduce the half-pixel interpolation errors.

  • an efficient re quantization error compensation for MPEG2 to h 264 transcoding
    International Symposium on Signal Processing and Information Technology, 2006
    Co-Authors: Qiang Tang, Panos Nasiopoulos, Rabab K Ward
    Abstract:

    During transcoding, the coefficients have to pass through another quantization step. This introduces re-quantization errors to the coefficients. H.264 integer transform and quantization features are different from those of MPEG2 and other standards. Based on these features, in MPEG2 to H.264 transcoding, an efficient algorithm that measures the re-quantization error is proposed. Then this measured error is used to compensate for the quality loss in transcoding. The experimental results from four typical video test sequences show that the proposed compensation procedure improves the PSNR value by about 4.82 dB. The error calculation and compensation could be carried in the transform domain resulting in significant computational saving.

  • Combining H.264 and MPEG2 for multi-resolution video applications
    Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513), 2004
    Co-Authors: D. Storey, Panos Nasiopoulos
    Abstract:

    The recent completion of the H.264 standard has opened new areas of research in the area of scalability. Spatial scalability for high definition sequences is particularly important, since future DVDs and broadcasts will undoubtedly be in high definition formats. In this paper, a new method of combining a low-resolution MPEG2 base layer with a high-resolution H.264 enhancement layer is explored. For a CIF sequence, the proposed scalability scheme offers bitrate savings (when compared to H.264 alone) of up to 54%, depending on the bitrate of the MPEG2 base layer.

  • An MPEG2-to-atm Converter To Optimize Performance Of Vbr Video Broadcast Over Atm Networks
    IEEE Transactions on Consumer Electronics, 1998
    Co-Authors: P.c.m. Wong, Victor C. M. Leung, Panos Nasiopoulos
    Abstract:

    This paper presents a novel MPEG2-to-ATM converter for VBR video broadcast over ATM networks. It functions as an external post-coding source rate controller between any MPEG2 source and an ATM network. Dynamic break points are employed to shape and partition the video data into high priority ATM cells which conform to the prevailing usage parameter control contract with the network, and nonconforming low priority cells which minimize the effects of cell loss due to network congestion on the subjective quality of the received video. Both high and low priority cells are transmitted over a common ATM virtual connection. Performance evaluations of actual VBR MPEG2 streams transmitted over a simulated converter and ATM network are presented to demonstrate the effectiveness of the proposed method.

Toshiyuki Araki - One of the best experts on this subject based on the ideXlab platform.

  • a 100 mm sup 2 0 95 w single chip MPEG2 mp ml video encoder with a 128gops motion estimator and a multi tasking risc type controller
    International Solid-State Circuits Conference, 1998
    Co-Authors: Eiji Miyagoshi, Toshiyuki Araki, Takuya Sayama, Akihiko Ohtani, Takayuki Minemaru, K Okamoto, Hisashi Kodama, Takayuki Morishige, Akihiro Watabe, Katsuji Aoki
    Abstract:

    A single-chip MPEG2 video encoder, VDSP3, has ten cores. All cores are executed in a macroblock-level pipeline similar to that of a previous LSI, VDSP2. The VIF transfers input video data in MPEG format. The ME1 and ME2 functions form a two-step, motion-estimation process. The MSP calculates statistical values for mode selection. The DCTQ performs the forward and inverse functions for both the DCT and quantization. The VLC outputs MPEG2 video streams. The CIF supports both constant-rate and DMA outputs of PES packets. The ERISC controls each core and is capable of performing rate control. The CLKCTL, with a PLL, supplies clock pulses to each core adaptively. The MSP, DCTQ and VLC are modified VDSP2 cores. By using the VDSP3, an MPEG2 MP@ML video encoder system can be realized with two 16 Mb SDRAMs controlled by the MIF in the VDSP3. Regions for the input image, re-ordering, local decoded image and video bit buffer (VBB) are mapped onto the SDRAMs.

  • a motion estimation processor for MPEG2 video real time encoding at wide search range
    Custom Integrated Circuits Conference, 1995
    Co-Authors: Akihiko Ohtani, Toshiyuki Araki, Katsuji Aoki, Yoshifumi Matsumoto, Masahiro Gion, Hisato Yoshida, Atsushi Ubukata, M Serizawa, Akira Sota, A Nagata
    Abstract:

    We have developed a motion estimation processor, named COMET (COmpact Motion Estimation processor for real-Time MPEG2 encoding) for real-time MPEG2 encoding. COMET contains a full pel resolution estimation processor made up of 256 processing elements, a half pel resolution estimation processor made up of 8 processing elements and an SDRAM interface. This chip searches motion vectors through a full search method in a horizontal and vertical range of -16 pel to +15.5 pel. COMET is implemented by using 0.5 /spl mu/m-CMOS technology and contains 1.5 million transistors on an area of 12.9 mm/spl times/11.1 mm. COMET has a computation power of 42GOPS at 80 MHz and performs real-time motion vector estimation at a speed of 54 MHz for 720 /spl times/480 pel. An MPEG2 real-time encoding system with a high quality image for MP@ML can be realized using COMET.

  • video dsp architecture for MPEG2 codec
    International Conference on Acoustics Speech and Signal Processing, 1994
    Co-Authors: Toshiyuki Araki, B. Wilson, M Toyokura, Toshihide Akiyama, H Takeno, Kunitoshi Aono
    Abstract:

    We developed a DSP named VDSP2 (Video Digital Signal Processor version 2) for MPEG2 video coding and decoding. In order to obtain the necessary performance, we employed a 2-level parallel processing scheme consisting of a pipeline processing at the macro block level and a parallel vector processing using a SIMD configuration at the block level. In the VDSP2, we included a DSP core which execute 4 parallel vector operations and scalar operations, a DRAM controller, a DCT/IDCT circuit, a VLC/VLD circuit including a programmable controller and a data communication circuit. As a result, the real-time encoder specified in MPEG2 can be realized with two VDSP2 chips, and the decoder can be realized with one VDSP2 chip. >

  • ICASSP (2) - Video DSP architecture for MPEG2 codec
    Proceedings of ICASSP '94. IEEE International Conference on Acoustics Speech and Signal Processing, 1994
    Co-Authors: Toshiyuki Araki, B. Wilson, M Toyokura, Toshihide Akiyama, H Takeno, Kunitoshi Aono
    Abstract:

    We developed a DSP named VDSP2 (Video Digital Signal Processor version 2) for MPEG2 video coding and decoding. In order to obtain the necessary performance, we employed a 2-level parallel processing scheme consisting of a pipeline processing at the macro block level and a parallel vector processing using a SIMD configuration at the block level. In the VDSP2, we included a DSP core which execute 4 parallel vector operations and scalar operations, a DRAM controller, a DCT/IDCT circuit, a VLC/VLD circuit including a programmable controller and a data communication circuit. As a result, the real-time encoder specified in MPEG2 can be realized with two VDSP2 chips, and the decoder can be realized with one VDSP2 chip. >

Takao Onoye - One of the best experts on this subject based on the ideXlab platform.

  • Implementation of half-pel precision motion estimator for MPEG2 MP@HL
    Proceedings of Digital Processing Applications (TENCON '96), 1996
    Co-Authors: Fujita, Takao Onoye, Isao Shirakawa, Shuji Tsukiyama, K. Matsumura
    Abstract:

    A half-pel precision single chip motion estimator is described dedicatedly for MPEG2 MP@HL moving pictures. Adopting a two-level hierarchical searching algorithm and the maximum possible reuse mechanism of reference pixels, MP@HL motion estimation is successfully facilitated. The broadcasting type PE array is used both for integer-pel precision vector and half-pel precision vector search processes. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip, which contains 1450 K transistors on a 12.7/spl times/13.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables real time motion estimation for MPEG2 MP@HL.

  • Architecture for MPEG2 MP@HL real time motion estimator
    1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, 1996
    Co-Authors: Takao Onoye, Fujita, Isao Shirakawa, K. Matsumura, Hiromu Ariyoshi, Shuji Tsukiyama
    Abstract:

    A VLSI architecture of a motion estimator is proposed, dedicated to MPEG2 MP@HL, which adopts a two-level hierarchical searching algorithm in detecting motion vectors. A novel mechanism is introduced into the full-search procedure which attempts the maximum possible reuse of reference pixels to reduce the bandwidth of frame memory interface. The proposed architecture has been integrated into a 0.6 /spl mu/m triple-metal CMOS chip which contains 1200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.

  • VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL
    Proceedings of Custom Integrated Circuits Conference, 1996
    Co-Authors: Takao Onoye, Fujita, Isao Shirakawa, K. Matsumura, Hiromu Ariyoshi, Shuji Tsukiyama
    Abstract:

    A VLSI motion estimator dedicated to MPEG2 MP@HL has been developed. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip which contains 1,200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.

  • hdtv level MPEG2 video decoder vlsi
    International Conference on Microelectronics, 1995
    Co-Authors: Takao Onoye, Toshihiro Masaki, Yasuo Morimoto, Yoh Sato, Isao Shirakawa
    Abstract:

    A novel architecture for an HDTV level MPEG2 decoder is developed, which consists of specific functional macrocells and macroblock level pipeline buffers. Owing to the sophisticated I/O interface among macrocells, macroblock level pipeline buffers are successfully incorporated with functional macrocells. A new organization of frame memory and interface is also devised. The designed decoder contains 454 K transistors, and occupies 81.0 mm/sup 2/ with a 0.6 /spl mu/m triple-metal CMOS technology.

  • vlsi implementation of inverse discrete cosine transformer and motion compensator for MPEG2 hdtv video decoding
    IEEE Transactions on Circuits and Systems for Video Technology, 1995
    Co-Authors: Toshihiro Masaki, Takao Onoye, Yasuo Morimoto, Isao Shirakawa
    Abstract:

    An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm/sup 2/ by a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock within 3.84 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) images in real time. >

Makoto Endo - One of the best experts on this subject based on the ideXlab platform.

  • a memory based architecture for MPEG2 system protocol lsis
    IEEE Transactions on Very Large Scale Integration Systems, 1999
    Co-Authors: M Inamori, Jiro Naganuma, Makoto Endo
    Abstract:

    This paper proposes a memory-based architecture implementing the MPEG2 system protocol large scale integrations (LSIs), and demonstrates its flexibility and performance. The memory-based architecture implements the full functionality of the MPEG2 system protocol for both multiplexing and demultiplexing MPEG2-encoded streams. It consists of a core central processing unit, memories, and dedicated application-specific hardware. It is designed and optimized by hardware/software codesign techniques. The LSI's provide sufficient performance and flexibility for real-time application of the MPEG2 system protocol. They were fabricated with 0.5 /spl mu/m CMOS embedded gate array process technology. They are now in use on MPEG2 codec systems for several multimedia communication and storage services.

  • Polling-based real-time software for MPEG2 System protocol LSIs
    Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference, 1997
    Co-Authors: Jiro Naganuma, Makoto Endo
    Abstract:

    This paper proposes polling-based real-time software for MPEG2 System protocol LSIs, which is a typical embedded and real-time system on a chip, and demonstrates its performance and usefulness. The polling-based real-time software is designed and optimized by analyzing application specific function requirements and deciding scheduling intervals and the execution cycles of each task. It requires neither hardware for multiple interrupt handling nor software for heavy context switching. The polling-based approach provides sufficient performance without any hardware and software overhead for a real-time application like the MPEG2 System protocol.

  • ED&TC - A memory-based architecture for MPEG2 System protocol LSIs
    Proceedings ED&TC European Design and Test Conference, 1996
    Co-Authors: M Inamori, Jiro Naganuma, Haruo Wakabayashi, Makoto Endo
    Abstract:

    This paper proposes a memory-based architecture implementing the MPEG2 System protocol LSIs, and demonstrates its flexibility and performance. The memory-based architecture implements the full functionality of the MPEG2 System protocol for both multiplexing and de-multiplexing MPEG2-encoded streams. It consists of a core CPU, memories, and dedicated application-specific hardware. It is designed and optimized by hardware/software co-design techniques. The LSIs provide sufficient performance and flexibility for real-time applications of the MPEG2 System protocol.

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