The Experts below are selected from a list of 3066 Experts worldwide ranked by ideXlab platform
Fat Duen Ho - One of the best experts on this subject based on the ideXlab platform.
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A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR Gate and the CMOS Nand Gate
2005 IEEE International Symposium on Circuits and Systems, 2005Co-Authors: M.w. Payton, Fat Duen HoAbstract:The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of our papers (part II), the results of using our model described in the companion paper (submitted to ibid) to simulate the CMOS NOR Gate and Nand Gate are presented. The numerical methods discussed in the companion paper are applied in the simulations for the NOR Gate and the Nand Gate. In addition, a bisection root finding algorithm is used to calculate any junction voltage that appears between two devices connected in series. The results compared well with those obtained from the SPICE level 3 and SPICE level 7 (BSIM 3.1) for a wide range of device geometries and circuit loading conditions. The results show that our model is capable of accurately simulating the transient response of devices with channel lengths as small as 0.33 /spl mu/m and for switching frequencies approaching 1 GHz.
M.w. Payton - One of the best experts on this subject based on the ideXlab platform.
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A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR Gate and the CMOS Nand Gate
2005 IEEE International Symposium on Circuits and Systems, 2005Co-Authors: M.w. Payton, Fat Duen HoAbstract:The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of our papers (part II), the results of using our model described in the companion paper (submitted to ibid) to simulate the CMOS NOR Gate and Nand Gate are presented. The numerical methods discussed in the companion paper are applied in the simulations for the NOR Gate and the Nand Gate. In addition, a bisection root finding algorithm is used to calculate any junction voltage that appears between two devices connected in series. The results compared well with those obtained from the SPICE level 3 and SPICE level 7 (BSIM 3.1) for a wide range of device geometries and circuit loading conditions. The results show that our model is capable of accurately simulating the transient response of devices with channel lengths as small as 0.33 /spl mu/m and for switching frequencies approaching 1 GHz.
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ISCAS (6) - A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR Gate and the CMOS Nand Gate
2005 IEEE International Symposium on Circuits and Systems, 2005Co-Authors: M.w. Payton, Fat D. HoAbstract:The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of our papers (part II), the results of using our model described in the companion paper (submitted to ibid) to simulate the CMOS NOR Gate and Nand Gate are presented. The numerical methods discussed in the companion paper are applied in the simulations for the NOR Gate and the Nand Gate. In addition, a bisection root finding algorithm is used to calculate any junction voltage that appears between two devices connected in series. The results compared well with those obtained from the SPICE level 3 and SPICE level 7 (BSIM 3.1) for a wide range of device geometries and circuit loading conditions. The results show that our model is capable of accurately simulating the transient response of devices with channel lengths as small as 0.33 /spl mu/m and for switching frequencies approaching 1 GHz.
Amer Kotb - One of the best experts on this subject based on the ideXlab platform.
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1 Tb/s high quality factor Nand Gate using quantum-dot semiconductor optical amplifiers in Mach---Zehnder interferometer
Journal of Computational Electronics, 2014Co-Authors: Amer Kotb, Kyriakos E. ZoirosAbstract:The performance of all-optical logic Nand Gate realized by employing quantum-dot semiconductor optical amplifiers (QD-SOAs)-based Mach---Zehnder interferometers (MZI) is numerically simulated. Boolean Nand operation is achieved by a series combination of properly configured and driven QD-SOAs-MZIs. The theoretical study is carried out by taking into account the effect of amplified spontaneous emission. The dependence of the output $$Q$$ Q -factor on data signals and QD-SOA parameters is investiGated and discussed. The obtained results indicate that the Nand Gate is capable of operating at 1 Tb/s with high output quality factor ( $$Q$$ Q -factor) provided that these parameters are properly optimized.
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Nand Gate with quantum dot-semiconductor optical amplifiers-based Mach-Zehnder interferometer
Optoelectronics Letters, 2013Co-Authors: Amer KotbAbstract:The Nand operation at 250 Gbit/s based on quantum dot-semiconductor optical amplifiers (QD-SOAs) is modeled. By solving the rate equations of SOAs in the form of a Mach-Zehnder interferometer (MZI), the performance of Nand Gate is numerically investiGated. The model takes the effects of amplified spontaneous emission (ASE) and the input pulse energy on the system’s quality factor into account. Results show that Nand Gate in QD-SOA-MZI based structure is feasible at 250 Gbit/s with a proper quality factor. The decrease in quality factor is predicted for high spontaneous emission factor ( N _SP). For an ideal amplifier ( N _SP = 2), the Q-factor is 17.8 for 30 dB gain.
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All optical logic Nand Gate based on two-photon absorption
Photonic Fiber and Crystal Devices: Advances in Materials and Innovations in Device Applications IV, 2010Co-Authors: Amer Kotb, Shaozhen Ma, Zhe Chen, Niloy K. Dutta, G. SaidAbstract:When the two-photon absorption of a high intensity pump beam takes place in a semiconductor optical amplifier there is an associated fast phase change of a weak probe signal. A scheme to realize fast all-optical Nand logic function using two-photon absorption induced phase change has been analyzed. Nand Gate is important because other Boolean logic elements and circuits can be demonstrated using Nand Gates as a basic building block. Rate equations for semiconductor optical amplifiers (for input data signals with high intensity) configured in the form of a Mach-Zehnder interferometer has been solved. The input intensities are high enough so that the two-photon induced phase change is larger than the regular gain induced phase change. The model shows that both AND and Nand operation at 250 Gb/s with good signal to noise ratio is feasible.
Min Zhang - One of the best experts on this subject based on the ideXlab platform.
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all optical Nand Gate using integrated soa based mach zehnder interferometer
Optical Fiber Technology, 2006Co-Authors: Xiaohua Ye, Peida Ye, Min ZhangAbstract:Abstract An all-optical Nand Gate using integrated SOA-based Mach–Zehnder interferometer is proposed and demonstrated for the first time. Numerical analysis shows the switching window of the proposed Nand Gate, which is synchronous with the dynamic gain experienced by the probe pulses. The effects of the SOA and input data parameters on the switching performance are discussed. The operation of the proposed Nand Gate with 10 Gb/s RZ pseudorandom bit sequences is simulated and the results demonstrate its effectiveness. This Nand Gate could provide a new possibility for all-optical routing in future all-optical networks.
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All-optical Nand Gate using integrated SOA-based Mach–Zehnder interferometer
Optical Fiber Technology, 2006Co-Authors: Xiaohua Ye, Peida Ye, Min ZhangAbstract:Abstract An all-optical Nand Gate using integrated SOA-based Mach–Zehnder interferometer is proposed and demonstrated for the first time. Numerical analysis shows the switching window of the proposed Nand Gate, which is synchronous with the dynamic gain experienced by the probe pulses. The effects of the SOA and input data parameters on the switching performance are discussed. The operation of the proposed Nand Gate with 10 Gb/s RZ pseudorandom bit sequences is simulated and the results demonstrate its effectiveness. This Nand Gate could provide a new possibility for all-optical routing in future all-optical networks.
Fat D. Ho - One of the best experts on this subject based on the ideXlab platform.
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Measurement and Analysis of a Ferroelectric Field-Effect Transistor Nand Gate
2009Co-Authors: Thomas A. Phillips, Todd C. Macleond, Rana Sayyah, Fat D. HoAbstract:Previous research investiGated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteristics that give them interesting and useful properties in digital logic circuits. The Nand Gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In this paper, Nand Gate circuits were constructed utilizing individual FFETs. N-channel FFETs with positive polarization were used for the standard CMOS Nand Gate n-channel transistors and n-channel FFETs with negative polarization were used for the standard CMOS Nand Gate p-channel transistors. The voltage transfer curves were obtained for the Nand Gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully operational circuits that would interface with existing logic circuits, but as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for these devices are presented, and their potential benefits and drawbacks are discussed. Vdd M3 MFSFET M4 (Neg. Polarized) MFSFET — — (Neg. Polarized) Vout M2 V MFSFET B — (Pos. Polarized) M1 V MFSFET A (Pos. Polarized) Figure 1: 2-Input MFSFET Nand Gate 0.0 1.0 2.0 3.0 4.0 5.0 B.0 Vin Figure 2: Voltage Transfer Curve for MFSFET Inverter 5 0 0.0 1.0 2.0 3.0 4.0 5.0 B.0 Vin Figure 3: Voltage Transfer Curve for 2-Input MFSFET Nand Gate
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METAL-FERROELECTRIC-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR Nand Gate SWITCHING TIME ANALYSIS
Integrated Ferroelectrics, 2007Co-Authors: Thomas A. Phillips, Todd C. Macleod, Fat D. HoAbstract:ABSTRACT Previous research investiGated the modeling of a Nand Gate constructed of n-channel Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. This paper investiGates the MFSFET Nand Gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic Gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input Nand Gate was analyzed similarly to the inverter Gate.
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Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor Nand Gate
Ferroelectrics, 2006Co-Authors: Thomas A. Phillips, Todd C. Macleod, Fat D. HoAbstract:The modeling of a Nand Gate constructed of Metal-Ferroelectric-Semiconductor Field Effect Transistors (MFSFETs) has been investiGated. Initially, an inverter circuit was modeled using a n-channel MFSFET with positive polarization for a standard CMOS inverter n-channel transistor and a n-channel MFSFET with negative polarization for the standard CMOS inverter p-channel transistor. The MFSFETs were simulated by using a previously developed MFSFET model which utilized a partitioned ferroelectric layer. Then a 2-input Nand Gate was modeled similar to the inverter Gate. The data shows that it is feasible to construct a Nand Gate with MFSFET transistors.
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ISCAS (6) - A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR Gate and the CMOS Nand Gate
2005 IEEE International Symposium on Circuits and Systems, 2005Co-Authors: M.w. Payton, Fat D. HoAbstract:The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of our papers (part II), the results of using our model described in the companion paper (submitted to ibid) to simulate the CMOS NOR Gate and Nand Gate are presented. The numerical methods discussed in the companion paper are applied in the simulations for the NOR Gate and the Nand Gate. In addition, a bisection root finding algorithm is used to calculate any junction voltage that appears between two devices connected in series. The results compared well with those obtained from the SPICE level 3 and SPICE level 7 (BSIM 3.1) for a wide range of device geometries and circuit loading conditions. The results show that our model is capable of accurately simulating the transient response of devices with channel lengths as small as 0.33 /spl mu/m and for switching frequencies approaching 1 GHz.
